Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v
H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Mon Sep 30 13:50:32 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.426s, Peak memory usage = 119.828MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 119.828MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 119.828MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 119.828MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 119.828MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 119.828MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 119.828MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 119.828MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 119.828MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 119.828MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 119.828MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 119.828MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 145.184MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 145.184MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 145.184MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 145.184MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 212
I/O Buf 212
    IBUF 211
    OBUF 1
Register 1118
    DFFRE 1
    DFFPE 36
    DFFCE 1081
LUT 719
    LUT2 61
    LUT3 135
    LUT4 523
MUX 1
    MUX16 1
ALU 14
    ALU 14
INV 4
    INV 4
BSRAM 23
    SDPX9B 23
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 745(731 LUT, 14 ALU) / 138240 <1%
Register 1118 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 1118 / 139095 <1%
BSRAM 23 / 340 7%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
cfg_clk Base 10.000 100.0 0.000 5.000 cfg_clk_ibuf/I
u_icon_top/n31_6 Base 10.000 100.0 0.000 5.000 u_icon_top/n31_s2/O
u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 cfg_clk 100.000(MHz) 166.910(MHz) 6 TOP
2 u_icon_top/n31_6 100.000(MHz) 1164.484(MHz) 1 TOP
3 u_la0_top/n15_6 100.000(MHz) 1164.484(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.009
Data Arrival Time 6.775
Data Required Time 10.784
From u_la0_top/u_ao_match_1/matched_s1
To u_la0_top/trigger_seq_start_s1
Launch Clk cfg_clk[R]
Latch Clk cfg_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 1 cfg_clk_ibuf/I
0.683 0.683 tINS RR 523 cfg_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s1/CLK
1.477 0.382 tC2Q RR 2 u_la0_top/u_ao_match_1/matched_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/n7688_s6/I0
2.469 0.579 tINS RR 1 u_la0_top/n7688_s6/F
2.881 0.413 tNET RR 1 u_la0_top/n7688_s4/I2
3.389 0.507 tINS RR 1 u_la0_top/n7688_s4/F
3.801 0.413 tNET RR 1 u_la0_top/n7688_s2/I0
4.380 0.579 tINS RR 3 u_la0_top/n7688_s2/F
4.793 0.413 tNET RR 1 u_la0_top/n7688_s1/I0
5.371 0.579 tINS RR 2 u_la0_top/n7688_s1/F
5.784 0.413 tNET RR 1 u_la0_top/trigger_seq_start_s3/I0
6.363 0.579 tINS RR 1 u_la0_top/trigger_seq_start_s3/F
6.775 0.413 tNET RR 1 u_la0_top/trigger_seq_start_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cfg_clk
10.000 0.000 tCL RR 1 cfg_clk_ibuf/I
10.682 0.683 tINS RR 523 cfg_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/trigger_seq_start_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/trigger_seq_start_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.823, 49.692%; route: 2.475, 43.574%; tC2Q: 0.382, 6.734%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 2

Path Summary:
Slack 4.080
Data Arrival Time 6.704
Data Required Time 10.784
From u_la0_top/u_ao_match_1/matched_s1
To u_la0_top/u_ao_match_1/match_cnt_0_s1
Launch Clk cfg_clk[R]
Latch Clk cfg_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 1 cfg_clk_ibuf/I
0.683 0.683 tINS RR 523 cfg_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s1/CLK
1.477 0.382 tC2Q RR 2 u_la0_top/u_ao_match_1/matched_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/n7688_s6/I0
2.469 0.579 tINS RR 1 u_la0_top/n7688_s6/F
2.881 0.413 tNET RR 1 u_la0_top/n7688_s4/I2
3.389 0.507 tINS RR 1 u_la0_top/n7688_s4/F
3.801 0.413 tNET RR 1 u_la0_top/n7688_s2/I0
4.380 0.579 tINS RR 3 u_la0_top/n7688_s2/F
4.793 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s6/I0
5.371 0.579 tINS RR 3 u_la0_top/u_ao_match_1/matched_s6/F
5.784 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_9_s3/I2
6.291 0.507 tINS RR 10 u_la0_top/u_ao_match_1/match_cnt_9_s3/F
6.704 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cfg_clk
10.000 0.000 tCL RR 1 cfg_clk_ibuf/I
10.682 0.683 tINS RR 523 cfg_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_0_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/u_ao_match_1/match_cnt_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.751, 49.053%; route: 2.475, 44.127%; tC2Q: 0.382, 6.820%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 3

Path Summary:
Slack 4.080
Data Arrival Time 6.704
Data Required Time 10.784
From u_la0_top/u_ao_match_1/matched_s1
To u_la0_top/u_ao_match_1/match_cnt_1_s1
Launch Clk cfg_clk[R]
Latch Clk cfg_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 1 cfg_clk_ibuf/I
0.683 0.683 tINS RR 523 cfg_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s1/CLK
1.477 0.382 tC2Q RR 2 u_la0_top/u_ao_match_1/matched_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/n7688_s6/I0
2.469 0.579 tINS RR 1 u_la0_top/n7688_s6/F
2.881 0.413 tNET RR 1 u_la0_top/n7688_s4/I2
3.389 0.507 tINS RR 1 u_la0_top/n7688_s4/F
3.801 0.413 tNET RR 1 u_la0_top/n7688_s2/I0
4.380 0.579 tINS RR 3 u_la0_top/n7688_s2/F
4.793 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s6/I0
5.371 0.579 tINS RR 3 u_la0_top/u_ao_match_1/matched_s6/F
5.784 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_9_s3/I2
6.291 0.507 tINS RR 10 u_la0_top/u_ao_match_1/match_cnt_9_s3/F
6.704 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cfg_clk
10.000 0.000 tCL RR 1 cfg_clk_ibuf/I
10.682 0.683 tINS RR 523 cfg_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_1_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/u_ao_match_1/match_cnt_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.751, 49.053%; route: 2.475, 44.127%; tC2Q: 0.382, 6.820%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 4

Path Summary:
Slack 4.080
Data Arrival Time 6.704
Data Required Time 10.784
From u_la0_top/u_ao_match_1/matched_s1
To u_la0_top/u_ao_match_1/match_cnt_2_s1
Launch Clk cfg_clk[R]
Latch Clk cfg_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 1 cfg_clk_ibuf/I
0.683 0.683 tINS RR 523 cfg_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s1/CLK
1.477 0.382 tC2Q RR 2 u_la0_top/u_ao_match_1/matched_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/n7688_s6/I0
2.469 0.579 tINS RR 1 u_la0_top/n7688_s6/F
2.881 0.413 tNET RR 1 u_la0_top/n7688_s4/I2
3.389 0.507 tINS RR 1 u_la0_top/n7688_s4/F
3.801 0.413 tNET RR 1 u_la0_top/n7688_s2/I0
4.380 0.579 tINS RR 3 u_la0_top/n7688_s2/F
4.793 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s6/I0
5.371 0.579 tINS RR 3 u_la0_top/u_ao_match_1/matched_s6/F
5.784 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_9_s3/I2
6.291 0.507 tINS RR 10 u_la0_top/u_ao_match_1/match_cnt_9_s3/F
6.704 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cfg_clk
10.000 0.000 tCL RR 1 cfg_clk_ibuf/I
10.682 0.683 tINS RR 523 cfg_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_2_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/u_ao_match_1/match_cnt_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.751, 49.053%; route: 2.475, 44.127%; tC2Q: 0.382, 6.820%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 5

Path Summary:
Slack 4.080
Data Arrival Time 6.704
Data Required Time 10.784
From u_la0_top/u_ao_match_1/matched_s1
To u_la0_top/u_ao_match_1/match_cnt_3_s1
Launch Clk cfg_clk[R]
Latch Clk cfg_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 1 cfg_clk_ibuf/I
0.683 0.683 tINS RR 523 cfg_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s1/CLK
1.477 0.382 tC2Q RR 2 u_la0_top/u_ao_match_1/matched_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/n7688_s6/I0
2.469 0.579 tINS RR 1 u_la0_top/n7688_s6/F
2.881 0.413 tNET RR 1 u_la0_top/n7688_s4/I2
3.389 0.507 tINS RR 1 u_la0_top/n7688_s4/F
3.801 0.413 tNET RR 1 u_la0_top/n7688_s2/I0
4.380 0.579 tINS RR 3 u_la0_top/n7688_s2/F
4.793 0.413 tNET RR 1 u_la0_top/u_ao_match_1/matched_s6/I0
5.371 0.579 tINS RR 3 u_la0_top/u_ao_match_1/matched_s6/F
5.784 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_9_s3/I2
6.291 0.507 tINS RR 10 u_la0_top/u_ao_match_1/match_cnt_9_s3/F
6.704 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cfg_clk
10.000 0.000 tCL RR 1 cfg_clk_ibuf/I
10.682 0.683 tINS RR 523 cfg_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_match_1/match_cnt_3_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/u_ao_match_1/match_cnt_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.751, 49.053%; route: 2.475, 44.127%; tC2Q: 0.382, 6.820%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%