Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\arb\arbiter_encryption.v H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\gowin_pll\gowin_pll.v H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\include\top_define.v H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\pcie\tlp_dec_encrypt.v H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\serdes\pcie_controller\pcie_controller.v H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\serdes\serdes.v H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\top.v |
| GowinSynthesis Constraints File | H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\pcie_dma_demo.gsc |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Mon Sep 30 13:49:40 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 323.656MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.339s, Peak memory usage = 323.656MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.139s, Peak memory usage = 323.656MB Optimizing Phase 2: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.349s, Peak memory usage = 323.656MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 323.656MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 323.656MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 323.656MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 323.656MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.368s, Peak memory usage = 323.656MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 323.656MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 323.656MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 323.656MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.326s, Peak memory usage = 323.656MB Generate output files: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.583s, Peak memory usage = 323.656MB |
| Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 323.656MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 23 |
| I/O Buf | 16 |
| IBUF | 2 |
| OBUF | 13 |
| TLVDS_IBUF | 1 |
| Register | 5414 |
| DFFSE | 12 |
| DFFRE | 1249 |
| DFFPE | 25 |
| DFFCE | 4128 |
| LUT | 2839 |
| LUT2 | 140 |
| LUT3 | 1345 |
| LUT4 | 1354 |
| ALU | 409 |
| ALU | 409 |
| INV | 151 |
| INV | 151 |
| BSRAM | 30 |
| SDPB | 21 |
| SDPX9B | 9 |
| CLOCK | 1 |
| CLKDIV | 1 |
| GTR12_PMAC | 1 |
| GTR12_QUAD | 1 |
| GTR12_UPAR | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3399(2990 LUT, 409 ALU) / 138240 | 3% |
| Register | 5414 / 139095 | 4% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 5414 / 139095 | 4% |
| BSRAM | 30 / 340 | 9% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| uut_div2/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | DEFAULT_CLK | uut_div2/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | uut_div2/CLKOUT.default_gen_clk | 50.000(MHz) | 104.712(MHz) | 12 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 10.450 |
| Data Arrival Time | 10.234 |
| Data Required Time | 20.684 |
| From | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0 |
| To | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1 |
| Launch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q |
| 1.543 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1 |
| 2.143 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT |
| 2.143 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN |
| 2.387 | 0.244 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/SUM |
| 2.799 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/I1 |
| 3.399 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/COUT |
| 3.399 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/CIN |
| 3.449 | 0.050 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/COUT |
| 3.449 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/CIN |
| 3.499 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/COUT |
| 3.499 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/CIN |
| 3.549 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/COUT |
| 3.549 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/CIN |
| 3.599 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/COUT |
| 3.599 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/CIN |
| 3.649 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/COUT |
| 3.649 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/CIN |
| 3.699 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/COUT |
| 3.699 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/CIN |
| 3.749 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT |
| 3.749 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN |
| 3.799 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT |
| 3.799 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN |
| 3.849 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT |
| 3.849 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN |
| 3.899 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT |
| 3.899 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN |
| 3.949 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT |
| 3.949 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN |
| 3.999 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT |
| 3.999 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN |
| 4.049 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT |
| 4.049 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN |
| 4.099 | 0.050 | tINS | RR | 3 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT |
| 4.512 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2 |
| 5.019 | 0.507 | tINS | RR | 13 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F |
| 5.432 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0 |
| 6.011 | 0.579 | tINS | RR | 6 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F |
| 6.423 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2 |
| 6.931 | 0.507 | tINS | RR | 5 | chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F |
| 7.343 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3092_s1/I1 |
| 7.911 | 0.567 | tINS | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n3092_s1/F |
| 8.323 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3090_s1/I2 |
| 8.831 | 0.507 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3090_s1/F |
| 9.243 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3090_s0/I0 |
| 9.822 | 0.579 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3090_s0/F |
| 10.234 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 20.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 20.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1/CLK |
| 20.684 | -0.064 | tSu | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 5.391, 56.832%; route: 3.712, 39.136%; tC2Q: 0.382, 4.032% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 11.329 |
| Data Arrival Time | 9.356 |
| Data Required Time | 20.684 |
| From | chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1 |
| To | chn_loop_j[0].u_tlp_rc/req_dma_wr_len_r_7_s1 |
| Launch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/CLK |
| 1.131 | 0.382 | tC2Q | RR | 4 | chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q |
| 1.543 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s73/I0 |
| 2.122 | 0.579 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s73/F |
| 2.534 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s72/I1 |
| 3.102 | 0.567 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s72/F |
| 3.514 | 0.413 | tNET | RR | 2 | chn_loop_j[0].u_tlp_rc/one_rc_over_s48/I0 |
| 4.109 | 0.595 | tINS | RF | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s48/COUT |
| 4.109 | 0.000 | tNET | FF | 2 | chn_loop_j[0].u_tlp_rc/one_rc_over_s49/CIN |
| 4.159 | 0.050 | tINS | FR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s49/COUT |
| 4.159 | 0.000 | tNET | RR | 2 | chn_loop_j[0].u_tlp_rc/one_rc_over_s50/CIN |
| 4.209 | 0.050 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s50/COUT |
| 4.209 | 0.000 | tNET | RR | 2 | chn_loop_j[0].u_tlp_rc/one_rc_over_s51/CIN |
| 4.259 | 0.050 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s51/COUT |
| 4.259 | 0.000 | tNET | RR | 2 | chn_loop_j[0].u_tlp_rc/one_rc_over_s52/CIN |
| 4.309 | 0.050 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s52/COUT |
| 4.309 | 0.000 | tNET | RR | 2 | chn_loop_j[0].u_tlp_rc/one_rc_over_s53/CIN |
| 4.359 | 0.050 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/one_rc_over_s53/COUT |
| 4.772 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/I3 |
| 5.061 | 0.289 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/F |
| 5.473 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/I1 |
| 6.041 | 0.567 | tINS | RR | 18 | chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/F |
| 6.453 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_7_s/I2 |
| 6.961 | 0.507 | tINS | RR | 3 | chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_7_s/F |
| 7.373 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/n1288_s8/I0 |
| 7.952 | 0.579 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/n1288_s8/F |
| 8.364 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/n1288_s7/I0 |
| 8.943 | 0.579 | tINS | RR | 1 | chn_loop_j[0].u_tlp_rc/n1288_s7/F |
| 9.356 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/req_dma_wr_len_r_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 20.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 20.748 | 0.413 | tNET | RR | 1 | chn_loop_j[0].u_tlp_rc/req_dma_wr_len_r_7_s1/CLK |
| 20.684 | -0.064 | tSu | 1 | chn_loop_j[0].u_tlp_rc/req_dma_wr_len_r_7_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.512, 52.425%; route: 3.712, 43.131%; tC2Q: 0.382, 4.444% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 11.359 |
| Data Arrival Time | 9.326 |
| Data Required Time | 20.684 |
| From | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0 |
| To | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1 |
| Launch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q |
| 1.543 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1 |
| 2.143 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT |
| 2.143 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN |
| 2.387 | 0.244 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/SUM |
| 2.799 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/I1 |
| 3.399 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/COUT |
| 3.399 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/CIN |
| 3.449 | 0.050 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/COUT |
| 3.449 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/CIN |
| 3.499 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/COUT |
| 3.499 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/CIN |
| 3.549 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/COUT |
| 3.549 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/CIN |
| 3.599 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/COUT |
| 3.599 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/CIN |
| 3.649 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/COUT |
| 3.649 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/CIN |
| 3.699 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/COUT |
| 3.699 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/CIN |
| 3.749 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT |
| 3.749 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN |
| 3.799 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT |
| 3.799 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN |
| 3.849 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT |
| 3.849 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN |
| 3.899 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT |
| 3.899 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN |
| 3.949 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT |
| 3.949 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN |
| 3.999 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT |
| 3.999 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN |
| 4.049 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT |
| 4.049 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN |
| 4.099 | 0.050 | tINS | RR | 3 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT |
| 4.512 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2 |
| 5.019 | 0.507 | tINS | RR | 13 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F |
| 5.432 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0 |
| 6.011 | 0.579 | tINS | RR | 6 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F |
| 6.423 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3096_s1/I0 |
| 7.002 | 0.579 | tINS | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n3096_s1/F |
| 7.414 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3094_s2/I2 |
| 7.922 | 0.507 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3094_s2/F |
| 8.334 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3094_s0/I0 |
| 8.913 | 0.579 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3094_s0/F |
| 9.326 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 20.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 20.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1/CLK |
| 20.684 | -0.064 | tSu | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.895, 57.068%; route: 3.300, 38.473%; tC2Q: 0.382, 4.459% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 11.370 |
| Data Arrival Time | 9.314 |
| Data Required Time | 20.684 |
| From | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0 |
| To | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_6_s1 |
| Launch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q |
| 1.543 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1 |
| 2.143 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT |
| 2.143 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN |
| 2.387 | 0.244 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/SUM |
| 2.799 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/I1 |
| 3.399 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/COUT |
| 3.399 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/CIN |
| 3.449 | 0.050 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/COUT |
| 3.449 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/CIN |
| 3.499 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/COUT |
| 3.499 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/CIN |
| 3.549 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/COUT |
| 3.549 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/CIN |
| 3.599 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/COUT |
| 3.599 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/CIN |
| 3.649 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/COUT |
| 3.649 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/CIN |
| 3.699 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/COUT |
| 3.699 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/CIN |
| 3.749 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT |
| 3.749 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN |
| 3.799 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT |
| 3.799 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN |
| 3.849 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT |
| 3.849 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN |
| 3.899 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT |
| 3.899 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN |
| 3.949 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT |
| 3.949 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN |
| 3.999 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT |
| 3.999 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN |
| 4.049 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT |
| 4.049 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN |
| 4.099 | 0.050 | tINS | RR | 3 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT |
| 4.512 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2 |
| 5.019 | 0.507 | tINS | RR | 13 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F |
| 5.432 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0 |
| 6.011 | 0.579 | tINS | RR | 6 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F |
| 6.423 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3098_s1/I2 |
| 6.931 | 0.507 | tINS | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n3098_s1/F |
| 7.343 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3097_s1/I1 |
| 7.911 | 0.567 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3097_s1/F |
| 8.323 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3097_s0/I0 |
| 8.902 | 0.579 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3097_s0/F |
| 9.314 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_6_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 20.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 20.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_6_s1/CLK |
| 20.684 | -0.064 | tSu | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_6_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.884, 57.012%; route: 3.300, 38.523%; tC2Q: 0.382, 4.465% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 11.370 |
| Data Arrival Time | 9.314 |
| Data Required Time | 20.684 |
| From | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0 |
| To | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1 |
| Launch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div2/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q |
| 1.543 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1 |
| 2.143 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT |
| 2.143 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN |
| 2.387 | 0.244 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/SUM |
| 2.799 | 0.413 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/I1 |
| 3.399 | 0.600 | tINS | RF | 1 | chn_loop_i[0].u_tlp_cpld_dec/n363_s0/COUT |
| 3.399 | 0.000 | tNET | FF | 2 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/CIN |
| 3.449 | 0.050 | tINS | FR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n364_s0/COUT |
| 3.449 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/CIN |
| 3.499 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n365_s0/COUT |
| 3.499 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/CIN |
| 3.549 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n366_s0/COUT |
| 3.549 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/CIN |
| 3.599 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n367_s0/COUT |
| 3.599 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/CIN |
| 3.649 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n368_s0/COUT |
| 3.649 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/CIN |
| 3.699 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n369_s0/COUT |
| 3.699 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/CIN |
| 3.749 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT |
| 3.749 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN |
| 3.799 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT |
| 3.799 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN |
| 3.849 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT |
| 3.849 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN |
| 3.899 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT |
| 3.899 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN |
| 3.949 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT |
| 3.949 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN |
| 3.999 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT |
| 3.999 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN |
| 4.049 | 0.050 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT |
| 4.049 | 0.000 | tNET | RR | 2 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN |
| 4.099 | 0.050 | tINS | RR | 3 | chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT |
| 4.512 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2 |
| 5.019 | 0.507 | tINS | RR | 13 | chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F |
| 5.432 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0 |
| 6.011 | 0.579 | tINS | RR | 6 | chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F |
| 6.423 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2 |
| 6.931 | 0.507 | tINS | RR | 5 | chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F |
| 7.343 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3088_s2/I1 |
| 7.911 | 0.567 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3088_s2/F |
| 8.323 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3088_s0/I0 |
| 8.902 | 0.579 | tINS | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/n3088_s0/F |
| 9.314 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | uut_div2/CLKOUT.default_gen_clk | |||
| 20.336 | 0.336 | tCL | RR | 5475 | uut_div2/CLKOUT |
| 20.748 | 0.413 | tNET | RR | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1/CLK |
| 20.684 | -0.064 | tSu | 1 | chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.884, 57.012%; route: 3.300, 38.523%; tC2Q: 0.382, 4.465% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |