Timing Messages

Report Title	Timing Analysis Report
Design File	H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\impl\gwsynthesis\pcie_dma_demo.vg
Physical Constraints File	H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\dvk_cfg_v2.cst
Timing Constraint File	H:\01_gaoyun\02_gowin5a_138\pcie\pcie_dma_demo_240306\pcie_dma_demo\src\pcie_dma_demo.sdc
Tool Version	V1.9.9.01 (64-bit)
Part Number	GW5AT-LV138PG484AC1/I0
Device	GW5AT-138
Device Version	B
Created Time	Mon Sep 30 13:53:57 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C1/I0
Hold Delay Model	Fast 0.945V 85C C1/I0
Numbers of Paths Analyzed	14880
Numbers of Endpoints Analyzed	25020
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	102
Numbers of Hold Violated Endpoints	1

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
div_clk	Base	10.000	100.000	0.000	5.000			uut_div2/CLKOUT
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	div_clk	100.000(MHz)	83.934(MHz)	12	TOP
2	tck_pad_i	20.000(MHz)	49.679(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
div_clk	Setup	-65.096	102
div_clk	Hold	-0.274	1
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.914	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1/D	div_clk:[R]	div_clk:[R]	10.000	-0.008	11.859
2	-1.829	chn_loop_j[0].u_tlp_rc/rc_wr_fsm_2_s1/Q	u_tl_tx/p_buf_wr_s0/D	div_clk:[R]	div_clk:[R]	10.000	0.019	11.746
3	-1.751	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_14_s1/D	div_clk:[R]	div_clk:[R]	10.000	-0.025	11.713
4	-1.656	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_12_s1/D	div_clk:[R]	div_clk:[R]	10.000	-0.018	11.610
5	-1.629	u_tl_tx/port_sel_1_s0/Q	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_5_s/DI[11]	div_clk:[R]	div_clk:[R]	10.000	0.024	11.570
6	-1.622	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_5_s0/D	div_clk:[R]	div_clk:[R]	10.000	0.027	11.531
7	-1.613	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_11_s1/D	div_clk:[R]	div_clk:[R]	10.000	-0.008	11.558
8	-1.601	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_1_s0/D	div_clk:[R]	div_clk:[R]	10.000	0.008	11.529
9	-1.582	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1/D	div_clk:[R]	div_clk:[R]	10.000	0.047	11.471
10	-1.562	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1/D	div_clk:[R]	div_clk:[R]	10.000	-0.008	11.506
11	-1.450	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_10_s1/D	div_clk:[R]	div_clk:[R]	10.000	-0.025	11.411
12	-1.441	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/D	div_clk:[R]	div_clk:[R]	10.000	0.008	11.369
13	-1.378	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_3_s0/D	div_clk:[R]	div_clk:[R]	10.000	0.003	11.311
14	-1.261	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_173_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.044	10.994
15	-1.261	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_174_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.044	10.994
16	-1.258	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_188_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.047	10.994
17	-1.245	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q	chn_loop_j[0].u_tlp_rc/rc_tlp_hdr_101_s0/D	div_clk:[R]	div_clk:[R]	10.000	-0.048	11.229
18	-1.044	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_185_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.049	10.782
19	-1.044	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_190_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.049	10.782
20	-1.042	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_175_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.054	10.785
21	-1.042	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_176_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.054	10.785
22	-1.042	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_177_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.054	10.785
23	-1.042	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_186_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.054	10.785
24	-1.040	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_189_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.056	10.785
25	-1.040	u_tl_tx/cpl_sel_3_s0/Q	u_tl_tx/cpl_buf_di_191_s1/CE	div_clk:[R]	div_clk:[R]	10.000	-0.056	10.785

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.274	u_tl_tx/rDataValid_s1/Q	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[2]	div_clk:[R]	div_clk:[R]	0.000	-0.012	1.156
2	0.023	u_tl_tx/rDataValid_s1/Q	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[7]	div_clk:[R]	div_clk:[R]	0.000	-0.012	1.327
3	0.049	u_cmd_if/req_dma_rd_addr_l_r[0]_25_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[23]	div_clk:[R]	div_clk:[R]	0.000	0.001	0.296
4	0.049	u_cmd_if/req_dma_rd_addr_l_r[0]_24_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[22]	div_clk:[R]	div_clk:[R]	0.000	0.001	0.296
5	0.049	u_cmd_if/req_dma_rd_len_r[0]_12_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[10]	div_clk:[R]	div_clk:[R]	0.000	0.002	0.296
6	0.049	u_cmd_if/req_dma_rd_len_r[0]_11_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[9]	div_clk:[R]	div_clk:[R]	0.000	0.002	0.296
7	0.053	u_cmd_if/req_dma_rd_addr_l_r[0]_30_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[28]	div_clk:[R]	div_clk:[R]	0.000	0.006	0.296
8	0.054	u_cmd_if/req_dma_wr_addr_l_r[0]_3_s0/Q	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[1]	div_clk:[R]	div_clk:[R]	0.000	0.006	0.296
9	0.058	u_cmd_if/req_dma_rd_addr_h_r[0]_19_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[17]	div_clk:[R]	div_clk:[R]	0.000	0.011	0.296
10	0.058	u_cmd_if/req_dma_rd_addr_h_r[0]_18_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[16]	div_clk:[R]	div_clk:[R]	0.000	0.011	0.296
11	0.062	u_cmd_if/req_dma_rd_addr_l_r[0]_19_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[17]	div_clk:[R]	div_clk:[R]	0.000	0.007	0.304
12	0.062	u_cmd_if/req_dma_rd_addr_l_r[0]_18_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[16]	div_clk:[R]	div_clk:[R]	0.000	0.007	0.304
13	0.062	u_cmd_if/req_dma_rd_addr_h_r[0]_29_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[27]	div_clk:[R]	div_clk:[R]	0.000	0.015	0.296
14	0.067	u_cmd_if/req_dma_wr_addr_l_r[0]_6_s0/Q	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[4]	div_clk:[R]	div_clk:[R]	0.000	0.012	0.304
15	0.076	u_cmd_if/req_dma_rd_addr_h_r[0]_27_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[25]	div_clk:[R]	div_clk:[R]	0.000	0.021	0.304
16	0.106	u_cmd_if/req_dma_wr_addr_l_r[0]_25_s0/Q	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[23]	div_clk:[R]	div_clk:[R]	0.000	0.001	0.354
17	0.106	u_cmd_if/req_dma_rd_addr_l_r[0]_23_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[21]	div_clk:[R]	div_clk:[R]	0.000	0.001	0.354
18	0.111	u_cmd_if/req_dma_rd_len_r[0]_6_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[4]	div_clk:[R]	div_clk:[R]	0.000	0.006	0.354
19	0.113	u_tl_tx/rDataValid_s1/Q	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[5]	div_clk:[R]	div_clk:[R]	0.000	-0.012	1.327
20	0.139	u_tl_tx/rDataValid_s1/Q	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[0]	div_clk:[R]	div_clk:[R]	0.000	-0.012	1.421
21	0.156	u_cmd_if/req_dma_rd_addr_l_r[0]_21_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[19]	div_clk:[R]	div_clk:[R]	0.000	0.007	0.397
22	0.156	u_cmd_if/req_dma_rd_addr_l_r[0]_20_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[18]	div_clk:[R]	div_clk:[R]	0.000	0.007	0.397
23	0.157	u_cmd_if/req_dma_rd_len_r[0]_19_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[17]	div_clk:[R]	div_clk:[R]	0.000	0.008	0.397
24	0.157	u_cmd_if/req_dma_rd_len_r[0]_16_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[14]	div_clk:[R]	div_clk:[R]	0.000	0.008	0.397
25	0.157	u_cmd_if/req_dma_rd_len_r[0]_15_s0/Q	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[13]	div_clk:[R]	div_clk:[R]	0.000	0.008	0.397

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.633	pcie_st_cnt_8_s0/Q	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_7_s/RESET	div_clk:[R]	div_clk:[R]	10.000	0.061	10.134
2	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_3/match_sep_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
3	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
4	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
5	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_2/match_bitwise_pre_reg_0_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
6	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_1/match_cnt_1_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
7	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_1/trig_dly_in_1_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
8	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
9	-0.268	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.921
10	-0.237	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_0_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.889
11	-0.237	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_1_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.889
12	-0.237	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_2_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.889
13	-0.237	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_3_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.889
14	-0.076	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	div_clk:[F]	div_clk:[R]	5.000	0.000	4.728
15	-0.076	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.728
16	-0.003	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.656
17	-0.003	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.656
18	-0.003	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.656
19	-0.003	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.656
20	-0.003	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.656
21	-0.004	pcie_st_cnt_8_s0/Q	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_6_s/RESET	div_clk:[R]	div_clk:[R]	10.000	0.061	9.505
22	0.000	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_1_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.653
23	0.000	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_6_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.653
24	0.000	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_7_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.653
25	0.000	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_10_s1/CLEAR	div_clk:[F]	div_clk:[R]	5.000	0.000	4.653

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.322	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_st/key_1_s0/Q	u_pcie_ctrl/gtr12_pmac_inst/FABRIC_TL_NPOR	div_clk:[R]	div_clk:[R]	0.000	-0.033	0.985
2	0.514	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_addr_l_r_0_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.335
3	0.514	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_addr_l_r_4_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.335
4	0.514	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_hdr_2_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.335
5	0.514	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_hdr_6_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.335
6	0.514	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_hdr_34_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.335
7	0.519	pcie_st_cnt_8_s0/Q	u_cmd_if/addrb_6_s4/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.340
8	0.519	pcie_st_cnt_8_s0/Q	u_cmd_if/addrb_7_s4/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.340
9	0.519	pcie_st_cnt_8_s0/Q	u_cmd_if/addrb_8_s4/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.340
10	0.519	pcie_st_cnt_8_s0/Q	u_cmd_if/fsm_1_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.010	0.340
11	0.528	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_req_id_r_2_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.019	0.358
12	0.530	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_cmd_en_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.014	0.355
13	0.530	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_sop_r_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.014	0.355
14	0.596	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.005	0.412
15	0.596	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_2_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.005	0.412
16	0.596	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_3_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.005	0.412
17	0.599	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_7_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	0.002	0.409
18	0.620	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_4_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.003	0.435
19	0.620	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_5_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.003	0.435
20	0.620	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_6_s1/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.003	0.435
21	0.627	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_hdr_3_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.009	0.447
22	0.627	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_hdr_4_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.009	0.447
23	0.627	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_hdr_5_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.009	0.447
24	0.629	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_addr_l_r_1_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.007	0.447
25	0.629	pcie_st_cnt_8_s0/Q	u_tlp_dec/rx_tlp_addr_l_r_2_s0/CLEAR	div_clk:[R]	div_clk:[R]	0.000	-0.007	0.447

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.620	3.620	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s
2	2.620	3.620	1.000	High Pulse Width	div_clk	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
3	2.625	3.625	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_0_s
4	2.625	3.625	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_3_s
5	2.625	3.625	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_4_s
6	2.625	3.625	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_5_s
7	2.625	3.625	1.000	High Pulse Width	div_clk	u_cc_ctrl/u_sdp_mem/gen_bsram.Bram_gen_bsram.Bram_0_1_s
8	2.625	3.625	1.000	High Pulse Width	div_clk	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
9	2.625	3.625	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s
10	2.625	3.625	1.000	High Pulse Width	div_clk	chn_loop_i[0].u_tlp_rq/u_rq_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.914
Data Arrival Time	14.781
Data Required Time	12.867
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.277	1.019	tNET	RR	1	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2
12.568	0.291	tINS	RR	5	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F
13.607	1.039	tNET	RR	1	R12C90[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n3092_s1/I1
13.896	0.289	tINS	RR	2	R12C90[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n3092_s1/F
14.049	0.154	tNET	RR	1	R12C90[3][A]	chn_loop_i[0].u_tlp_cpld_dec/n3090_s1/I2
14.341	0.291	tINS	RR	1	R12C90[3][A]	chn_loop_i[0].u_tlp_cpld_dec/n3090_s1/F
14.492	0.151	tNET	RR	1	R12C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n3090_s0/I0
14.781	0.289	tINS	RR	1	R12C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n3090_s0/F
14.781	0.000	tNET	RR	1	R12C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.930	2.930	tNET	RR	1	R12C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1/CLK
12.867	-0.064	tSu		1	R12C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_13_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	10.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 3.831, 32.307%; route: 7.645, 64.467%; tC2Q: 0.382, 3.225%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%

Path2

Path Summary:

Slack	-1.829
Data Arrival Time	14.667
Data Required Time	12.837
From	chn_loop_j[0].u_tlp_rc/rc_wr_fsm_2_s1
To	u_tl_tx/p_buf_wr_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.921	2.921	tNET	RR	1	R38C102[1][A]	chn_loop_j[0].u_tlp_rc/rc_wr_fsm_2_s1/CLK
3.303	0.382	tC2Q	RR	19	R38C102[1][A]	chn_loop_j[0].u_tlp_rc/rc_wr_fsm_2_s1/Q
5.594	2.291	tNET	RR	1	R33C96[3][B]	chn_loop_j[0].u_tlp_rc/rc_hdr_en_s3/I1
6.142	0.548	tINS	RR	139	R33C96[3][B]	chn_loop_j[0].u_tlp_rc/rc_hdr_en_s3/F
7.362	1.220	tNET	RR	1	R34C105[3][A]	chn_loop_j[0].u_tlp_rc/rc_valid_wr_4_s7/I2
7.681	0.319	tINS	RF	2	R34C105[3][A]	chn_loop_j[0].u_tlp_rc/rc_valid_wr_4_s7/F
7.691	0.010	tNET	FF	1	R34C105[2][B]	chn_loop_j[0].u_tlp_rc/rc_valid_wr_4_s0/I3
8.198	0.507	tINS	FR	5	R34C105[2][B]	chn_loop_j[0].u_tlp_rc/rc_valid_wr_4_s0/F
11.882	3.684	tNET	RR	1	R11C102[3][B]	chn_loop_j[0].u_tlp_rc/rc_valid_wr_2_s0/I2
12.429	0.548	tINS	RR	2	R11C102[3][B]	chn_loop_j[0].u_tlp_rc/rc_valid_wr_2_s0/F
13.393	0.964	tNET	RR	1	R6C102[2][A]	u_tl_tx/n7316_s1/I2
13.972	0.579	tINS	RR	1	R6C102[2][A]	u_tl_tx/n7316_s1/F
14.378	0.406	tNET	RR	1	R6C99[0][B]	u_tl_tx/n7316_s0/I0
14.667	0.289	tINS	RR	1	R6C99[0][B]	u_tl_tx/n7316_s0/F
14.667	0.000	tNET	RR	1	R6C99[0][B]	u_tl_tx/p_buf_wr_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.901	2.901	tNET	RR	1	R6C99[0][B]	u_tl_tx/p_buf_wr_s0/CLK
12.837	-0.064	tSu		1	R6C99[0][B]	u_tl_tx/p_buf_wr_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.921, 100.000%
Arrival Data Path Delay	cell: 2.789, 23.742%; route: 8.575, 73.002%; tC2Q: 0.382, 3.256%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.901, 100.000%

Path3

Path Summary:

Slack	-1.751
Data Arrival Time	14.634
Data Required Time	12.883
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_14_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.277	1.019	tNET	RR	1	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2
12.568	0.291	tINS	RR	5	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F
13.776	1.207	tNET	RR	1	R11C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n3089_s1/I0
14.064	0.289	tINS	RR	1	R11C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n3089_s1/F
14.067	0.003	tNET	RR	1	R11C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n3089_s0/I2
14.634	0.567	tINS	RR	1	R11C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n3089_s0/F
14.634	0.000	tNET	RR	1	R11C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_14_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.947	2.947	tNET	RR	1	R11C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_14_s1/CLK
12.883	-0.064	tSu		1	R11C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_14_s1

Path Statistics:

Clock Skew	0.025
Setup Relationship	10.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 3.819, 32.604%; route: 7.511, 64.130%; tC2Q: 0.382, 3.266%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.947, 100.000%

Path4

Path Summary:

Slack	-1.656
Data Arrival Time	14.532
Data Required Time	12.876
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_12_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.277	1.019	tNET	RR	1	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2
12.568	0.291	tINS	RR	5	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F
13.629	1.061	tNET	RR	1	R12C91[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3091_s2/I2
13.948	0.319	tINS	RF	1	R12C91[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3091_s2/F
13.953	0.005	tNET	FF	1	R12C91[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n3091_s0/I0
14.532	0.579	tINS	FR	1	R12C91[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n3091_s0/F
14.532	0.000	tNET	RR	1	R12C91[0][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.940	2.940	tNET	RR	1	R12C91[0][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_12_s1/CLK
12.876	-0.064	tSu		1	R12C91[0][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_12_s1

Path Statistics:

Clock Skew	0.018
Setup Relationship	10.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 3.860, 33.247%; route: 7.368, 63.458%; tC2Q: 0.382, 3.295%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.940, 100.000%

Path5

Path Summary:

Slack	-1.629
Data Arrival Time	14.481
Data Required Time	12.852
From	u_tl_tx/port_sel_1_s0
To	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_5_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[0][B]	u_tl_tx/port_sel_1_s0/CLK
3.293	0.382	tC2Q	RR	537	R6C102[0][B]	u_tl_tx/port_sel_1_s0/Q
9.768	6.475	tNET	RR	1	R34C91[3][B]	u_tl_tx/buf_di_191_s1/I2
10.316	0.548	tINS	RR	1	R34C91[3][B]	u_tl_tx/buf_di_191_s1/F
11.028	0.713	tNET	RR	1	R33C92[1][B]	u_tl_tx/buf_di_191_s0/I2
11.317	0.289	tINS	RR	1	R33C92[1][B]	u_tl_tx/buf_di_191_s0/F
14.481	3.164	tNET	RR	1	BSRAM_R10[21]	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_5_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.887	2.887	tNET	RR	1	BSRAM_R10[21]	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_5_s/CLKA
12.852	-0.035	tSu		1	BSRAM_R10[21]	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_5_s

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.836, 7.228%; route: 10.351, 89.466%; tC2Q: 0.382, 3.306%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.887, 100.000%

Path6

Path Summary:

Slack	-1.622
Data Arrival Time	14.461
Data Required Time	12.839
From	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1
To	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_5_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.930	2.930	tNET	RR	1	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/CLK
3.312	0.382	tC2Q	RR	4	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q
4.332	1.020	tNET	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/I0
4.880	0.548	tINS	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/F
5.803	0.923	tNET	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/I1
6.310	0.507	tINS	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/F
7.729	1.419	tNET	RR	2	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/I0
8.324	0.595	tINS	RF	1	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/COUT
8.324	0.000	tNET	FF	2	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/CIN
8.374	0.050	tINS	FR	1	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/COUT
8.374	0.000	tNET	RR	2	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/CIN
8.424	0.050	tINS	RR	1	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/COUT
8.424	0.000	tNET	RR	2	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/CIN
8.474	0.050	tINS	RR	1	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/COUT
8.474	0.000	tNET	RR	2	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/CIN
8.524	0.050	tINS	RR	1	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/COUT
8.524	0.000	tNET	RR	2	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/CIN
8.574	0.050	tINS	RR	1	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/COUT
8.990	0.416	tNET	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/I3
9.446	0.456	tINS	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/F
9.619	0.172	tNET	RR	1	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/I1
9.938	0.319	tINS	RF	18	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/F
10.331	0.394	tNET	FF	1	R44C105[3][A]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_8_s/I2
10.905	0.574	tINS	FR	3	R44C105[3][A]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_8_s/F
14.461	3.556	tNET	RR	1	R17C92[3][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.903	2.903	tNET	RR	1	R17C92[3][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_5_s0/CLK
12.839	-0.064	tSu		1	R17C92[3][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_5_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%
Arrival Data Path Delay	cell: 3.249, 28.173%; route: 7.900, 68.509%; tC2Q: 0.382, 3.317%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.903, 100.000%

Path7

Path Summary:

Slack	-1.613
Data Arrival Time	14.479
Data Required Time	12.867
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_11_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.277	1.019	tNET	RR	1	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2
12.568	0.291	tINS	RR	5	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F
13.607	1.039	tNET	RR	1	R12C90[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n3092_s1/I1
13.896	0.289	tINS	RR	2	R12C90[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n3092_s1/F
13.901	0.005	tNET	RR	1	R12C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n3092_s0/I2
14.479	0.579	tINS	RR	1	R12C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n3092_s0/F
14.479	0.000	tNET	RR	1	R12C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.930	2.930	tNET	RR	1	R12C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_11_s1/CLK
12.867	-0.064	tSu		1	R12C90[1][B]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_11_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	10.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 3.830, 33.139%; route: 7.345, 63.552%; tC2Q: 0.382, 3.310%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%

Path8

Path Summary:

Slack	-1.601
Data Arrival Time	14.459
Data Required Time	12.858
From	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1
To	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_1_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.930	2.930	tNET	RR	1	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/CLK
3.312	0.382	tC2Q	RR	4	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q
4.332	1.020	tNET	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/I0
4.880	0.548	tINS	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/F
5.803	0.923	tNET	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/I1
6.310	0.507	tINS	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/F
7.729	1.419	tNET	RR	2	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/I0
8.324	0.595	tINS	RF	1	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/COUT
8.324	0.000	tNET	FF	2	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/CIN
8.374	0.050	tINS	FR	1	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/COUT
8.374	0.000	tNET	RR	2	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/CIN
8.424	0.050	tINS	RR	1	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/COUT
8.424	0.000	tNET	RR	2	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/CIN
8.474	0.050	tINS	RR	1	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/COUT
8.474	0.000	tNET	RR	2	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/CIN
8.524	0.050	tINS	RR	1	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/COUT
8.524	0.000	tNET	RR	2	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/CIN
8.574	0.050	tINS	RR	1	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/COUT
8.990	0.416	tNET	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/I3
9.446	0.456	tINS	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/F
9.619	0.172	tNET	RR	1	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/I1
9.910	0.291	tINS	RR	18	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/F
13.880	3.970	tNET	RR	1	R34C87[2][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_4_s/I0
14.459	0.579	tINS	RR	1	R34C87[2][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_4_s/F
14.459	0.000	tNET	RR	1	R34C87[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.922	2.922	tNET	RR	1	R34C87[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_1_s0/CLK
12.858	-0.064	tSu		1	R34C87[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_1_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%
Arrival Data Path Delay	cell: 3.226, 27.984%; route: 7.920, 68.698%; tC2Q: 0.382, 3.318%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path9

Path Summary:

Slack	-1.582
Data Arrival Time	14.393
Data Required Time	12.811
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.657	1.399	tNET	RR	1	R16C93[3][A]	chn_loop_i[0].u_tlp_cpld_dec/n3096_s1/I0
12.976	0.319	tINS	RF	2	R16C93[3][A]	chn_loop_i[0].u_tlp_cpld_dec/n3096_s1/F
13.191	0.215	tNET	FF	1	R16C95[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3094_s2/I2
13.647	0.456	tINS	FR	1	R16C95[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3094_s2/F
13.819	0.172	tNET	RR	1	R17C95[3][A]	chn_loop_i[0].u_tlp_cpld_dec/n3094_s0/I0
14.393	0.574	tINS	RR	1	R17C95[3][A]	chn_loop_i[0].u_tlp_cpld_dec/n3094_s0/F
14.393	0.000	tNET	RR	1	R17C95[3][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.875	2.875	tNET	RR	1	R17C95[3][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1/CLK
12.811	-0.064	tSu		1	R17C95[3][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_9_s1

Path Statistics:

Clock Skew	-0.047
Setup Relationship	10.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 4.020, 35.044%; route: 7.069, 61.621%; tC2Q: 0.382, 3.334%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.875, 100.000%

Path10

Path Summary:

Slack	-1.562
Data Arrival Time	14.428
Data Required Time	12.867
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.277	1.019	tNET	RR	1	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2
12.568	0.291	tINS	RR	5	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F
13.629	1.061	tNET	RR	1	R12C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n3088_s2/I1
13.918	0.289	tINS	RR	1	R12C90[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n3088_s2/F
13.921	0.003	tNET	RR	1	R12C90[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n3088_s0/I0
14.428	0.507	tINS	RR	1	R12C90[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n3088_s0/F
14.428	0.000	tNET	RR	1	R12C90[0][B]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.930	2.930	tNET	RR	1	R12C90[0][B]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1/CLK
12.867	-0.064	tSu		1	R12C90[0][B]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_15_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	10.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 3.759, 32.667%; route: 7.365, 64.009%; tC2Q: 0.382, 3.324%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%

Path11

Path Summary:

Slack	-1.450
Data Arrival Time	14.333
Data Required Time	12.883
From	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
To	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_10_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
3.304	0.382	tC2Q	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/Q
5.511	2.206	tNET	RR	2	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/I1
6.056	0.545	tINS	RR	1	R17C92[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_0_s/COUT
6.056	0.000	tNET	RR	2	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/CIN
6.106	0.050	tINS	RR	1	R17C92[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_1_s/COUT
6.106	0.000	tNET	RR	2	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/CIN
6.156	0.050	tINS	RR	1	R17C92[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_2_s/COUT
6.156	0.000	tNET	RR	2	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/CIN
6.206	0.050	tINS	RR	1	R17C92[1][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_3_s/COUT
6.206	0.000	tNET	RR	2	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/CIN
6.256	0.050	tINS	RR	1	R17C92[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_4_s/COUT
6.256	0.000	tNET	RR	2	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/CIN
6.306	0.050	tINS	RR	1	R17C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_5_s/COUT
6.306	0.000	tNET	RR	2	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/CIN
6.356	0.050	tINS	RR	1	R17C93[0][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_6_s/COUT
6.356	0.000	tNET	RR	2	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/CIN
6.406	0.050	tINS	RR	1	R17C93[0][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_7_s/COUT
6.406	0.000	tNET	RR	2	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/CIN
6.649	0.244	tINS	RR	1	R17C93[1][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_addr_max_w_8_s/SUM
7.179	0.530	tNET	RR	2	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/I1
7.779	0.600	tINS	RF	1	R16C94[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n370_s0/COUT
7.779	0.000	tNET	FF	2	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/CIN
7.829	0.050	tINS	FR	1	R16C94[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n371_s0/COUT
7.829	0.000	tNET	RR	2	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/CIN
7.879	0.050	tINS	RR	1	R16C94[2][A]	chn_loop_i[0].u_tlp_cpld_dec/n372_s0/COUT
7.879	0.000	tNET	RR	2	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/CIN
7.929	0.050	tINS	RR	1	R16C94[2][B]	chn_loop_i[0].u_tlp_cpld_dec/n373_s0/COUT
7.929	0.000	tNET	RR	2	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/CIN
7.979	0.050	tINS	RR	1	R16C95[0][A]	chn_loop_i[0].u_tlp_cpld_dec/n374_s0/COUT
7.979	0.000	tNET	RR	2	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/CIN
8.029	0.050	tINS	RR	1	R16C95[0][B]	chn_loop_i[0].u_tlp_cpld_dec/n375_s0/COUT
8.029	0.000	tNET	RR	2	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/CIN
8.079	0.050	tINS	RR	1	R16C95[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n376_s0/COUT
8.079	0.000	tNET	RR	2	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/CIN
8.129	0.050	tINS	RR	3	R16C95[1][B]	chn_loop_i[0].u_tlp_cpld_dec/n377_s0/COUT
9.872	1.742	tNET	RR	1	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/I2
10.163	0.291	tINS	RR	13	R11C90[3][B]	chn_loop_i[0].u_tlp_cpld_dec/mrd_en_s2/F
10.967	0.804	tNET	RR	1	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/I0
11.258	0.291	tINS	RR	6	R15C87[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3100_s1/F
12.277	1.019	tNET	RR	1	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/I2
12.568	0.291	tINS	RR	5	R16C94[3][B]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s1/F
13.754	1.186	tNET	RR	1	R11C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s0/I2
14.333	0.579	tINS	RR	1	R11C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/n3093_s0/F
14.333	0.000	tNET	RR	1	R11C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.947	2.947	tNET	RR	1	R11C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_10_s1/CLK
12.883	-0.064	tSu		1	R11C90[1][A]	chn_loop_i[0].u_tlp_cpld_dec/mem_addrb_10_s1

Path Statistics:

Clock Skew	0.025
Setup Relationship	10.000
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%
Arrival Data Path Delay	cell: 3.541, 31.033%; route: 7.488, 65.615%; tC2Q: 0.382, 3.352%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.947, 100.000%

Path12

Path Summary:

Slack	-1.441
Data Arrival Time	14.299
Data Required Time	12.858
From	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1
To	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.930	2.930	tNET	RR	1	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/CLK
3.312	0.382	tC2Q	RR	4	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q
4.332	1.020	tNET	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/I0
4.880	0.548	tINS	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/F
5.803	0.923	tNET	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/I1
6.310	0.507	tINS	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/F
7.729	1.419	tNET	RR	2	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/I0
8.324	0.595	tINS	RF	1	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/COUT
8.324	0.000	tNET	FF	2	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/CIN
8.374	0.050	tINS	FR	1	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/COUT
8.374	0.000	tNET	RR	2	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/CIN
8.424	0.050	tINS	RR	1	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/COUT
8.424	0.000	tNET	RR	2	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/CIN
8.474	0.050	tINS	RR	1	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/COUT
8.474	0.000	tNET	RR	2	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/CIN
8.524	0.050	tINS	RR	1	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/COUT
8.524	0.000	tNET	RR	2	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/CIN
8.574	0.050	tINS	RR	1	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/COUT
8.990	0.416	tNET	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/I3
9.446	0.456	tINS	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/F
9.619	0.172	tNET	RR	1	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/I1
9.910	0.291	tINS	RR	18	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/F
13.731	3.821	tNET	RR	1	R34C87[2][A]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_3_s/I0
14.299	0.567	tINS	RR	1	R34C87[2][A]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_3_s/F
14.299	0.000	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.922	2.922	tNET	RR	1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0/CLK
12.858	-0.064	tSu		1	R34C87[2][A]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_0_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%
Arrival Data Path Delay	cell: 3.215, 28.279%; route: 7.771, 68.356%; tC2Q: 0.382, 3.364%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path13

Path Summary:

Slack	-1.378
Data Arrival Time	14.241
Data Required Time	12.863
From	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1
To	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_3_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.930	2.930	tNET	RR	1	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/CLK
3.312	0.382	tC2Q	RR	4	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q
4.332	1.020	tNET	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/I0
4.880	0.548	tINS	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/F
5.803	0.923	tNET	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/I1
6.310	0.507	tINS	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/F
7.729	1.419	tNET	RR	2	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/I0
8.324	0.595	tINS	RF	1	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/COUT
8.324	0.000	tNET	FF	2	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/CIN
8.374	0.050	tINS	FR	1	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/COUT
8.374	0.000	tNET	RR	2	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/CIN
8.424	0.050	tINS	RR	1	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/COUT
8.424	0.000	tNET	RR	2	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/CIN
8.474	0.050	tINS	RR	1	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/COUT
8.474	0.000	tNET	RR	2	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/CIN
8.524	0.050	tINS	RR	1	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/COUT
8.524	0.000	tNET	RR	2	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/CIN
8.574	0.050	tINS	RR	1	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/COUT
8.990	0.416	tNET	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/I3
9.446	0.456	tINS	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/F
9.619	0.172	tNET	RR	1	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/I1
9.938	0.319	tINS	RF	18	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/F
10.331	0.394	tNET	FF	1	R44C105[2][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_6_s/I2
10.899	0.567	tINS	FR	3	R44C105[2][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_6_s/F
14.241	3.342	tNET	RR	1	R25C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.927	2.927	tNET	RR	1	R25C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_3_s0/CLK
12.863	-0.064	tSu		1	R25C92[2][B]	chn_loop_i[0].u_tlp_cpld_dec/rc_curr_len_r_3_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%
Arrival Data Path Delay	cell: 3.242, 28.666%; route: 7.686, 67.952%; tC2Q: 0.382, 3.382%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.927, 100.000%

Path14

Path Summary:

Slack	-1.261
Data Arrival Time	13.904
Data Required Time	12.644
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_173_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.904	10.611	tNET	RR	1	R40C67[0][A]	u_tl_tx/cpl_buf_di_173_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.955	2.955	tNET	RR	1	R40C67[0][A]	u_tl_tx/cpl_buf_di_173_s1/CLK
12.644	-0.311	tSu		1	R40C67[0][A]	u_tl_tx/cpl_buf_di_173_s1

Path Statistics:

Clock Skew	0.044
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.611, 96.521%; tC2Q: 0.382, 3.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.955, 100.000%

Path15

Path Summary:

Slack	-1.261
Data Arrival Time	13.904
Data Required Time	12.644
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_174_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.904	10.611	tNET	RR	1	R40C67[0][B]	u_tl_tx/cpl_buf_di_174_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.955	2.955	tNET	RR	1	R40C67[0][B]	u_tl_tx/cpl_buf_di_174_s1/CLK
12.644	-0.311	tSu		1	R40C67[0][B]	u_tl_tx/cpl_buf_di_174_s1

Path Statistics:

Clock Skew	0.044
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.611, 96.521%; tC2Q: 0.382, 3.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.955, 100.000%

Path16

Path Summary:

Slack	-1.258
Data Arrival Time	13.904
Data Required Time	12.646
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_188_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.904	10.611	tNET	RR	1	R39C67[1][B]	u_tl_tx/cpl_buf_di_188_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.958	2.958	tNET	RR	1	R39C67[1][B]	u_tl_tx/cpl_buf_di_188_s1/CLK
12.646	-0.311	tSu		1	R39C67[1][B]	u_tl_tx/cpl_buf_di_188_s1

Path Statistics:

Clock Skew	0.047
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.611, 96.521%; tC2Q: 0.382, 3.479%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.958, 100.000%

Path17

Path Summary:

Slack	-1.245
Data Arrival Time	14.159
Data Required Time	12.914
From	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1
To	chn_loop_j[0].u_tlp_rc/rc_tlp_hdr_101_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.930	2.930	tNET	RR	1	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/CLK
3.312	0.382	tC2Q	RR	4	R38C105[2][A]	chn_loop_j[0].u_tlp_rc/rc_dma_len_tmp_3_s1/Q
4.332	1.020	tNET	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/I0
4.880	0.548	tINS	RR	1	R36C101[3][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s73/F
5.803	0.923	tNET	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/I1
6.310	0.507	tINS	RR	1	R39C102[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s72/F
7.729	1.419	tNET	RR	2	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/I0
8.324	0.595	tINS	RF	1	R45C105[0][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s48/COUT
8.324	0.000	tNET	FF	2	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/CIN
8.374	0.050	tINS	FR	1	R45C105[0][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s49/COUT
8.374	0.000	tNET	RR	2	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/CIN
8.424	0.050	tINS	RR	1	R45C105[1][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s50/COUT
8.424	0.000	tNET	RR	2	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/CIN
8.474	0.050	tINS	RR	1	R45C105[1][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s51/COUT
8.474	0.000	tNET	RR	2	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/CIN
8.524	0.050	tINS	RR	1	R45C105[2][A]	chn_loop_j[0].u_tlp_rc/one_rc_over_s52/COUT
8.524	0.000	tNET	RR	2	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/CIN
8.574	0.050	tINS	RR	1	R45C105[2][B]	chn_loop_j[0].u_tlp_rc/one_rc_over_s53/COUT
8.990	0.416	tNET	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/I3
9.446	0.456	tINS	RR	1	R45C107[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s4/F
9.619	0.172	tNET	RR	1	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/I1
9.938	0.319	tINS	RF	18	R45C106[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_4_s2/F
10.541	0.604	tNET	FF	1	R43C104[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_5_s/I2
11.089	0.548	tINS	FR	3	R43C104[3][B]	chn_loop_j[0].u_tlp_rc/rc_wr_req_len_Z_5_s/F
14.159	3.070	tNET	RR	1	R26C91[0][A]	chn_loop_j[0].u_tlp_rc/rc_tlp_hdr_101_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.978	2.978	tNET	RR	1	R26C91[0][A]	chn_loop_j[0].u_tlp_rc/rc_tlp_hdr_101_s0/CLK
12.914	-0.064	tSu		1	R26C91[0][A]	chn_loop_j[0].u_tlp_rc/rc_tlp_hdr_101_s0

Path Statistics:

Clock Skew	0.048
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.930, 100.000%
Arrival Data Path Delay	cell: 3.222, 28.699%; route: 7.624, 67.895%; tC2Q: 0.382, 3.406%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.978, 100.000%

Path18

Path Summary:

Slack	-1.044
Data Arrival Time	13.693
Data Required Time	12.649
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_185_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.693	10.400	tNET	RR	1	R38C67[0][B]	u_tl_tx/cpl_buf_di_185_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.960	2.960	tNET	RR	1	R38C67[0][B]	u_tl_tx/cpl_buf_di_185_s1/CLK
12.649	-0.311	tSu		1	R38C67[0][B]	u_tl_tx/cpl_buf_di_185_s1

Path Statistics:

Clock Skew	0.049
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.400, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.960, 100.000%

Path19

Path Summary:

Slack	-1.044
Data Arrival Time	13.693
Data Required Time	12.649
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_190_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.693	10.400	tNET	RR	1	R38C67[0][A]	u_tl_tx/cpl_buf_di_190_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.960	2.960	tNET	RR	1	R38C67[0][A]	u_tl_tx/cpl_buf_di_190_s1/CLK
12.649	-0.311	tSu		1	R38C67[0][A]	u_tl_tx/cpl_buf_di_190_s1

Path Statistics:

Clock Skew	0.049
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.400, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.960, 100.000%

Path20

Path Summary:

Slack	-1.042
Data Arrival Time	13.696
Data Required Time	12.653
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_175_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.696	10.402	tNET	RR	1	R40C68[1][B]	u_tl_tx/cpl_buf_di_175_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.964	2.964	tNET	RR	1	R40C68[1][B]	u_tl_tx/cpl_buf_di_175_s1/CLK
12.653	-0.311	tSu		1	R40C68[1][B]	u_tl_tx/cpl_buf_di_175_s1

Path Statistics:

Clock Skew	0.054
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.402, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.964, 100.000%

Path21

Path Summary:

Slack	-1.042
Data Arrival Time	13.696
Data Required Time	12.653
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_176_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.696	10.402	tNET	RR	1	R40C68[1][A]	u_tl_tx/cpl_buf_di_176_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.964	2.964	tNET	RR	1	R40C68[1][A]	u_tl_tx/cpl_buf_di_176_s1/CLK
12.653	-0.311	tSu		1	R40C68[1][A]	u_tl_tx/cpl_buf_di_176_s1

Path Statistics:

Clock Skew	0.054
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.402, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.964, 100.000%

Path22

Path Summary:

Slack	-1.042
Data Arrival Time	13.696
Data Required Time	12.653
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_177_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.696	10.402	tNET	RR	1	R40C68[0][B]	u_tl_tx/cpl_buf_di_177_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.964	2.964	tNET	RR	1	R40C68[0][B]	u_tl_tx/cpl_buf_di_177_s1/CLK
12.653	-0.311	tSu		1	R40C68[0][B]	u_tl_tx/cpl_buf_di_177_s1

Path Statistics:

Clock Skew	0.054
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.402, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.964, 100.000%

Path23

Path Summary:

Slack	-1.042
Data Arrival Time	13.696
Data Required Time	12.653
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_186_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.696	10.402	tNET	RR	1	R40C68[0][A]	u_tl_tx/cpl_buf_di_186_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.964	2.964	tNET	RR	1	R40C68[0][A]	u_tl_tx/cpl_buf_di_186_s1/CLK
12.653	-0.311	tSu		1	R40C68[0][A]	u_tl_tx/cpl_buf_di_186_s1

Path Statistics:

Clock Skew	0.054
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.402, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.964, 100.000%

Path24

Path Summary:

Slack	-1.040
Data Arrival Time	13.696
Data Required Time	12.656
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_189_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.696	10.402	tNET	RR	1	R39C68[0][B]	u_tl_tx/cpl_buf_di_189_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.967	2.967	tNET	RR	1	R39C68[0][B]	u_tl_tx/cpl_buf_di_189_s1/CLK
12.656	-0.311	tSu		1	R39C68[0][B]	u_tl_tx/cpl_buf_di_189_s1

Path Statistics:

Clock Skew	0.056
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.402, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.967, 100.000%

Path25

Path Summary:

Slack	-1.040
Data Arrival Time	13.696
Data Required Time	12.656
From	u_tl_tx/cpl_sel_3_s0
To	u_tl_tx/cpl_buf_di_191_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.911	2.911	tNET	RR	1	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/CLK
3.293	0.382	tC2Q	RR	266	R6C102[1][B]	u_tl_tx/cpl_sel_3_s0/Q
13.696	10.402	tNET	RR	1	R39C68[0][A]	u_tl_tx/cpl_buf_di_191_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.967	2.967	tNET	RR	1	R39C68[0][A]	u_tl_tx/cpl_buf_di_191_s1/CLK
12.656	-0.311	tSu		1	R39C68[0][A]	u_tl_tx/cpl_buf_di_191_s1

Path Statistics:

Clock Skew	0.056
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.911, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 10.402, 96.453%; tC2Q: 0.382, 3.547%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.967, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.274
Data Arrival Time	2.456
Data Required Time	2.731
From	u_tl_tx/rDataValid_s1
To	u_pcie_ctrl/gtr12_pmac_inst
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.300	1.300	tNET	RR	1	R9C91[1][A]	u_tl_tx/rDataValid_s1/CLK
1.480	0.180	tC2Q	RR	12	R9C91[1][A]	u_tl_tx/rDataValid_s1/Q
1.869	0.389	tNET	RR	1	R9C93[3][B]	u_tl_tx/tl_tx_valid_Z_2_s/I0
2.054	0.185	tINS	RR	2	R9C93[3][B]	u_tl_tx/tl_tx_valid_Z_2_s/F
2.456	0.402	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.312	1.312	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_CLKP
2.731	1.419	tHld		1	R0C38	u_pcie_ctrl/gtr12_pmac_inst

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.300, 100.000%
Arrival Data Path Delay	cell: 0.185, 16.000%; route: 0.791, 68.432%; tC2Q: 0.180, 15.568%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.312, 100.000%

Path2

Path Summary:

Slack	0.023
Data Arrival Time	2.627
Data Required Time	2.605
From	u_tl_tx/rDataValid_s1
To	u_pcie_ctrl/gtr12_pmac_inst
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.300	1.300	tNET	RR	1	R9C91[1][A]	u_tl_tx/rDataValid_s1/CLK
1.480	0.180	tC2Q	RR	12	R9C91[1][A]	u_tl_tx/rDataValid_s1/Q
2.001	0.521	tNET	RR	1	R9C95[2][A]	u_tl_tx/tl_tx_valid_Z_7_s/I0
2.319	0.317	tINS	RR	2	R9C95[2][A]	u_tl_tx/tl_tx_valid_Z_7_s/F
2.627	0.309	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.312	1.312	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_CLKP
2.605	1.293	tHld		1	R0C38	u_pcie_ctrl/gtr12_pmac_inst

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.300, 100.000%
Arrival Data Path Delay	cell: 0.317, 23.917%; route: 0.830, 62.524%; tC2Q: 0.180, 13.559%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.312, 100.000%

Path3

Path Summary:

Slack	0.049
Data Arrival Time	1.577
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_25_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.281	1.281	tNET	RR	1	R45C87[2][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_25_s0/CLK
1.461	0.180	tC2Q	RR	1	R45C87[2][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_25_s0/Q
1.577	0.116	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.281, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path4

Path Summary:

Slack	0.049
Data Arrival Time	1.577
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_24_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.281	1.281	tNET	RR	1	R45C87[2][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_24_s0/CLK
1.461	0.180	tC2Q	RR	1	R45C87[2][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_24_s0/Q
1.577	0.116	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[22]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.281, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path5

Path Summary:

Slack	0.049
Data Arrival Time	1.586
Data Required Time	1.537
From	u_cmd_if/req_dma_rd_len_r[0]_12_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.290	1.290	tNET	RR	1	R45C93[0][B]	u_cmd_if/req_dma_rd_len_r[0]_12_s0/CLK
1.470	0.180	tC2Q	RR	1	R45C93[0][B]	u_cmd_if/req_dma_rd_len_r[0]_12_s0/Q
1.586	0.116	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.288	1.288	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA
1.537	0.249	tHld		1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.288, 100.000%

Path6

Path Summary:

Slack	0.049
Data Arrival Time	1.586
Data Required Time	1.537
From	u_cmd_if/req_dma_rd_len_r[0]_11_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.290	1.290	tNET	RR	1	R45C93[1][A]	u_cmd_if/req_dma_rd_len_r[0]_11_s0/CLK
1.470	0.180	tC2Q	RR	1	R45C93[1][A]	u_cmd_if/req_dma_rd_len_r[0]_11_s0/Q
1.586	0.116	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.288	1.288	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA
1.537	0.249	tHld		1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.288, 100.000%

Path7

Path Summary:

Slack	0.053
Data Arrival Time	1.582
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_30_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.286	1.286	tNET	RR	1	R45C88[2][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_30_s0/CLK
1.466	0.180	tC2Q	RR	1	R45C88[2][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_30_s0/Q
1.582	0.116	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.286, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path8

Path Summary:

Slack	0.054
Data Arrival Time	1.586
Data Required Time	1.533
From	u_cmd_if/req_dma_wr_addr_l_r[0]_3_s0
To	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.290	1.290	tNET	RR	1	R45C101[2][B]	u_cmd_if/req_dma_wr_addr_l_r[0]_3_s0/CLK
1.470	0.180	tC2Q	RR	1	R45C101[2][B]	u_cmd_if/req_dma_wr_addr_l_r[0]_3_s0/Q
1.586	0.116	tNET	RR	1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.284	1.284	tNET	RR	1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.533	0.249	tHld		1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.284, 100.000%

Path9

Path Summary:

Slack	0.058
Data Arrival Time	1.592
Data Required Time	1.534
From	u_cmd_if/req_dma_rd_addr_h_r[0]_19_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.296	1.296	tNET	RR	1	R45C90[2][A]	u_cmd_if/req_dma_rd_addr_h_r[0]_19_s0/CLK
1.476	0.180	tC2Q	RR	1	R45C90[2][A]	u_cmd_if/req_dma_rd_addr_h_r[0]_19_s0/Q
1.592	0.116	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.285	1.285	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA
1.534	0.249	tHld		1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.296, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.285, 100.000%

Path10

Path Summary:

Slack	0.058
Data Arrival Time	1.592
Data Required Time	1.534
From	u_cmd_if/req_dma_rd_addr_h_r[0]_18_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.296	1.296	tNET	RR	1	R45C90[2][B]	u_cmd_if/req_dma_rd_addr_h_r[0]_18_s0/CLK
1.476	0.180	tC2Q	RR	1	R45C90[2][B]	u_cmd_if/req_dma_rd_addr_h_r[0]_18_s0/Q
1.592	0.116	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.285	1.285	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA
1.534	0.249	tHld		1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.296, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.285, 100.000%

Path11

Path Summary:

Slack	0.062
Data Arrival Time	1.591
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_19_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.287	1.287	tNET	RR	1	R44C87[2][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_19_s0/CLK
1.467	0.180	tC2Q	RR	1	R44C87[2][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_19_s0/Q
1.591	0.124	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.287, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path12

Path Summary:

Slack	0.062
Data Arrival Time	1.591
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_18_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.287	1.287	tNET	RR	1	R44C87[2][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_18_s0/CLK
1.467	0.180	tC2Q	RR	1	R44C87[2][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_18_s0/Q
1.591	0.124	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.287, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path13

Path Summary:

Slack	0.062
Data Arrival Time	1.596
Data Required Time	1.534
From	u_cmd_if/req_dma_rd_addr_h_r[0]_29_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.300	1.300	tNET	RR	1	R45C91[2][B]	u_cmd_if/req_dma_rd_addr_h_r[0]_29_s0/CLK
1.480	0.180	tC2Q	RR	1	R45C91[2][B]	u_cmd_if/req_dma_rd_addr_h_r[0]_29_s0/Q
1.596	0.116	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.285	1.285	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA
1.534	0.249	tHld		1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.300, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.285, 100.000%

Path14

Path Summary:

Slack	0.067
Data Arrival Time	1.600
Data Required Time	1.533
From	u_cmd_if/req_dma_wr_addr_l_r[0]_6_s0
To	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.296	1.296	tNET	RR	1	R44C101[3][A]	u_cmd_if/req_dma_wr_addr_l_r[0]_6_s0/CLK
1.476	0.180	tC2Q	RR	1	R44C101[3][A]	u_cmd_if/req_dma_wr_addr_l_r[0]_6_s0/Q
1.600	0.124	tNET	RR	1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.284	1.284	tNET	RR	1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.533	0.249	tHld		1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.296, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.284, 100.000%

Path15

Path Summary:

Slack	0.076
Data Arrival Time	1.610
Data Required Time	1.534
From	u_cmd_if/req_dma_rd_addr_h_r[0]_27_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.306	1.306	tNET	RR	1	R44C91[1][B]	u_cmd_if/req_dma_rd_addr_h_r[0]_27_s0/CLK
1.486	0.180	tC2Q	RR	1	R44C91[1][B]	u_cmd_if/req_dma_rd_addr_h_r[0]_27_s0/Q
1.610	0.124	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/DI[25]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.285	1.285	tNET	RR	1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA
1.534	0.249	tHld		1	BSRAM_R46[18][B]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.306, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.285, 100.000%

Path16

Path Summary:

Slack	0.106
Data Arrival Time	1.639
Data Required Time	1.533
From	u_cmd_if/req_dma_wr_addr_l_r[0]_25_s0
To	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.285	1.285	tNET	RR	1	R45C102[3][A]	u_cmd_if/req_dma_wr_addr_l_r[0]_25_s0/CLK
1.465	0.180	tC2Q	RR	1	R45C102[3][A]	u_cmd_if/req_dma_wr_addr_l_r[0]_25_s0/Q
1.639	0.174	tNET	RR	1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[23]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.284	1.284	tNET	RR	1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.533	0.249	tHld		1	BSRAM_R46[21][A]	chn_loop_j[0].u_tlp_rc/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.285, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 49.117%; tC2Q: 0.180, 50.883%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.284, 100.000%

Path17

Path Summary:

Slack	0.106
Data Arrival Time	1.635
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_23_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.281	1.281	tNET	RR	1	R45C87[3][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_23_s0/CLK
1.461	0.180	tC2Q	RR	1	R45C87[3][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_23_s0/Q
1.635	0.174	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[21]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.281, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 49.117%; tC2Q: 0.180, 50.883%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path18

Path Summary:

Slack	0.111
Data Arrival Time	1.648
Data Required Time	1.537
From	u_cmd_if/req_dma_rd_len_r[0]_6_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R45C92[3][A]	u_cmd_if/req_dma_rd_len_r[0]_6_s0/CLK
1.474	0.180	tC2Q	RR	1	R45C92[3][A]	u_cmd_if/req_dma_rd_len_r[0]_6_s0/Q
1.648	0.174	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.288	1.288	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA
1.537	0.249	tHld		1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 49.117%; tC2Q: 0.180, 50.883%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.288, 100.000%

Path19

Path Summary:

Slack	0.113
Data Arrival Time	2.627
Data Required Time	2.514
From	u_tl_tx/rDataValid_s1
To	u_pcie_ctrl/gtr12_pmac_inst
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.300	1.300	tNET	RR	1	R9C91[1][A]	u_tl_tx/rDataValid_s1/CLK
1.480	0.180	tC2Q	RR	12	R9C91[1][A]	u_tl_tx/rDataValid_s1/Q
2.001	0.521	tNET	RR	1	R9C95[0][B]	u_tl_tx/tl_tx_valid_Z_5_s/I0
2.319	0.317	tINS	RR	2	R9C95[0][B]	u_tl_tx/tl_tx_valid_Z_5_s/F
2.627	0.309	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.312	1.312	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_CLKP
2.514	1.202	tHld		1	R0C38	u_pcie_ctrl/gtr12_pmac_inst

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.300, 100.000%
Arrival Data Path Delay	cell: 0.317, 23.917%; route: 0.830, 62.524%; tC2Q: 0.180, 13.559%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.312, 100.000%

Path20

Path Summary:

Slack	0.139
Data Arrival Time	2.721
Data Required Time	2.583
From	u_tl_tx/rDataValid_s1
To	u_pcie_ctrl/gtr12_pmac_inst
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.300	1.300	tNET	RR	1	R9C91[1][A]	u_tl_tx/rDataValid_s1/CLK
1.480	0.180	tC2Q	RR	12	R9C91[1][A]	u_tl_tx/rDataValid_s1/Q
2.001	0.521	tNET	RR	1	R9C95[1][B]	u_tl_tx/tl_tx_valid_Z_0_s/I0
2.319	0.317	tINS	RR	2	R9C95[1][B]	u_tl_tx/tl_tx_valid_Z_0_s/F
2.721	0.402	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_TX_VALID0[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.312	1.312	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_CLKP
2.583	1.271	tHld		1	R0C38	u_pcie_ctrl/gtr12_pmac_inst

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.300, 100.000%
Arrival Data Path Delay	cell: 0.317, 22.339%; route: 0.924, 64.996%; tC2Q: 0.180, 12.665%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.312, 100.000%

Path21

Path Summary:

Slack	0.156
Data Arrival Time	1.685
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_21_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.287	1.287	tNET	RR	1	R44C87[1][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_21_s0/CLK
1.467	0.180	tC2Q	RR	1	R44C87[1][A]	u_cmd_if/req_dma_rd_addr_l_r[0]_21_s0/Q
1.685	0.217	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[19]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.287, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path22

Path Summary:

Slack	0.156
Data Arrival Time	1.685
Data Required Time	1.529
From	u_cmd_if/req_dma_rd_addr_l_r[0]_20_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.287	1.287	tNET	RR	1	R44C87[1][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_20_s0/CLK
1.467	0.180	tC2Q	RR	1	R44C87[1][B]	u_cmd_if/req_dma_rd_addr_l_r[0]_20_s0/Q
1.685	0.217	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/DI[18]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.280	1.280	tNET	RR	1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA
1.529	0.249	tHld		1	BSRAM_R46[18][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.287, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.280, 100.000%

Path23

Path Summary:

Slack	0.157
Data Arrival Time	1.694
Data Required Time	1.537
From	u_cmd_if/req_dma_rd_len_r[0]_19_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.296	1.296	tNET	RR	1	R44C93[0][B]	u_cmd_if/req_dma_rd_len_r[0]_19_s0/CLK
1.476	0.180	tC2Q	RR	1	R44C93[0][B]	u_cmd_if/req_dma_rd_len_r[0]_19_s0/Q
1.694	0.217	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.288	1.288	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA
1.537	0.249	tHld		1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.296, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.288, 100.000%

Path24

Path Summary:

Slack	0.157
Data Arrival Time	1.694
Data Required Time	1.537
From	u_cmd_if/req_dma_rd_len_r[0]_16_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.296	1.296	tNET	RR	1	R44C93[1][B]	u_cmd_if/req_dma_rd_len_r[0]_16_s0/CLK
1.476	0.180	tC2Q	RR	1	R44C93[1][B]	u_cmd_if/req_dma_rd_len_r[0]_16_s0/Q
1.694	0.217	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.288	1.288	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA
1.537	0.249	tHld		1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.296, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.288, 100.000%

Path25

Path Summary:

Slack	0.157
Data Arrival Time	1.694
Data Required Time	1.537
From	u_cmd_if/req_dma_rd_len_r[0]_15_s0
To	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.296	1.296	tNET	RR	1	R44C93[1][A]	u_cmd_if/req_dma_rd_len_r[0]_15_s0/CLK
1.476	0.180	tC2Q	RR	1	R44C93[1][A]	u_cmd_if/req_dma_rd_len_r[0]_15_s0/Q
1.694	0.217	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.288	1.288	tNET	RR	1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA
1.537	0.249	tHld		1	BSRAM_R46[19][A]	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.296, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.288, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.633
Data Arrival Time	13.081
Data Required Time	12.449
From	pcie_st_cnt_8_s0
To	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_7_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.947	2.947	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
3.315	0.368	tC2Q	RF	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
13.081	9.766	tNET	FF	32	BSRAM_R10[23]	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_7_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.887	2.887	tNET	RR	1	BSRAM_R10[23]	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_7_s/CLKB
12.449	-0.438	tSu		1	BSRAM_R10[23]	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_7_s

Path Statistics:

Clock Skew	-0.061
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.947, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 9.766, 96.374%; tC2Q: 0.368, 3.626%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.887, 100.000%

Path2

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_3/match_sep_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C6[0][A]	u_la0_top/u_ao_match_3/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C6[0][A]	u_la0_top/u_ao_match_3/match_sep_s0/CLK
9.653	-0.347	tSu		1	R11C6[0][A]	u_la0_top/u_ao_match_3/match_sep_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C6[0][B]	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0/CLK
9.653	-0.347	tSu		1	R11C6[0][B]	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C6[1][A]	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C6[1][A]	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0/CLK
9.653	-0.347	tSu		1	R11C6[1][A]	u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_2/match_bitwise_pre_reg_0_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C6[1][B]	u_la0_top/u_ao_match_2/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C6[1][B]	u_la0_top/u_ao_match_2/match_bitwise_pre_reg_0_s0/CLK
9.653	-0.347	tSu		1	R11C6[1][B]	u_la0_top/u_ao_match_2/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_1/match_cnt_1_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C6[2][A]	u_la0_top/u_ao_match_1/match_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C6[2][A]	u_la0_top/u_ao_match_1/match_cnt_1_s1/CLK
9.653	-0.347	tSu		1	R11C6[2][A]	u_la0_top/u_ao_match_1/match_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_1/trig_dly_in_1_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C5[1][A]	u_la0_top/u_ao_match_1/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C5[1][A]	u_la0_top/u_ao_match_1/trig_dly_in_1_s0/CLK
9.653	-0.347	tSu		1	R11C5[1][A]	u_la0_top/u_ao_match_1/trig_dly_in_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C5[0][A]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C5[0][A]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
9.653	-0.347	tSu		1	R11C5[0][A]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	-0.268
Data Arrival Time	9.921
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.921	4.478	tNET	FF	1	R11C5[0][B]	u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C5[0][B]	u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
9.653	-0.347	tSu		1	R11C5[0][B]	u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.478, 91.008%; tC2Q: 0.442, 8.992%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	-0.237
Data Arrival Time	9.889
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_0_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.889	4.447	tNET	FF	1	R11C2[3][B]	u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C2[3][B]	u_la0_top/triger_level_cnt_0_s1/CLK
9.653	-0.347	tSu		1	R11C2[3][B]	u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.447, 90.949%; tC2Q: 0.442, 9.051%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	-0.237
Data Arrival Time	9.889
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_1_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.889	4.447	tNET	FF	1	R11C2[3][A]	u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C2[3][A]	u_la0_top/triger_level_cnt_1_s1/CLK
9.653	-0.347	tSu		1	R11C2[3][A]	u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.447, 90.949%; tC2Q: 0.442, 9.051%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	-0.237
Data Arrival Time	9.889
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_2_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.889	4.447	tNET	FF	1	R11C2[2][B]	u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C2[2][B]	u_la0_top/triger_level_cnt_2_s1/CLK
9.653	-0.347	tSu		1	R11C2[2][B]	u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.447, 90.949%; tC2Q: 0.442, 9.051%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	-0.237
Data Arrival Time	9.889
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_3_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.889	4.447	tNET	FF	1	R11C2[2][A]	u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R11C2[2][A]	u_la0_top/triger_level_cnt_3_s1/CLK
9.653	-0.347	tSu		1	R11C2[2][A]	u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.447, 90.949%; tC2Q: 0.442, 9.051%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	-0.076
Data Arrival Time	9.728
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.728	4.286	tNET	FF	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
9.653	-0.347	tSu		1	R9C7[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.286, 90.642%; tC2Q: 0.442, 9.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	-0.076
Data Arrival Time	9.728
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.728	4.286	tNET	FF	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
9.653	-0.347	tSu		1	R9C7[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.286, 90.642%; tC2Q: 0.442, 9.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	-0.003
Data Arrival Time	9.656
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.656	4.213	tNET	FF	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
9.653	-0.347	tSu		1	R9C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.213, 90.496%; tC2Q: 0.442, 9.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	-0.003
Data Arrival Time	9.656
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.656	4.213	tNET	FF	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
9.653	-0.347	tSu		1	R9C9[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.213, 90.496%; tC2Q: 0.442, 9.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	-0.003
Data Arrival Time	9.656
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.656	4.213	tNET	FF	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
9.653	-0.347	tSu		1	R9C9[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.213, 90.496%; tC2Q: 0.442, 9.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack	-0.003
Data Arrival Time	9.656
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.656	4.213	tNET	FF	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
9.653	-0.347	tSu		1	R9C9[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.213, 90.496%; tC2Q: 0.442, 9.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack	-0.003
Data Arrival Time	9.656
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.656	4.213	tNET	FF	1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
9.653	-0.347	tSu		1	R9C9[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.213, 90.496%; tC2Q: 0.442, 9.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	-0.004
Data Arrival Time	12.453
Data Required Time	12.449
From	pcie_st_cnt_8_s0
To	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_6_s
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
2.947	2.947	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
3.315	0.368	tC2Q	RF	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
12.453	9.138	tNET	FF	36	BSRAM_R10[22][A]	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_6_s/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
12.887	2.887	tNET	RR	1	BSRAM_R10[22][A]	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_6_s/CLKB
12.449	-0.438	tSu		1	BSRAM_R10[22][A]	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_6_s

Path Statistics:

Clock Skew	-0.061
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.947, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 9.138, 96.134%; tC2Q: 0.368, 3.866%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.887, 100.000%

Path22

Path Summary:

Slack	0.000
Data Arrival Time	9.653
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_1_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.653	4.210	tNET	FF	1	R2C2[3][A]	u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R2C2[3][A]	u_la0_top/capture_window_sel_1_s1/CLK
9.653	-0.347	tSu		1	R2C2[3][A]	u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.210, 90.489%; tC2Q: 0.442, 9.511%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	0.000
Data Arrival Time	9.653
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_6_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.653	4.210	tNET	FF	1	R2C3[3][B]	u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R2C3[3][B]	u_la0_top/capture_window_sel_6_s1/CLK
9.653	-0.347	tSu		1	R2C3[3][B]	u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.210, 90.489%; tC2Q: 0.442, 9.511%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	0.000
Data Arrival Time	9.653
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_7_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.653	4.210	tNET	FF	1	R2C3[3][A]	u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R2C3[3][A]	u_la0_top/capture_window_sel_7_s1/CLK
9.653	-0.347	tSu		1	R2C3[3][A]	u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.210, 90.489%; tC2Q: 0.442, 9.511%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	0.000
Data Arrival Time	9.653
Data Required Time	9.653
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_10_s1
Launch Clk	div_clk:[F]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					div_clk
5.000	0.000	tCL	FF	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
5.000	0.000	tNET	FF	1	R9C8[2][A]	u_la0_top/rst_ao_s0/CLK
5.443	0.442	tC2Q	FF	91	R9C8[2][A]	u_la0_top/rst_ao_s0/Q
9.653	4.210	tNET	FF	1	R2C2[3][B]	u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					div_clk
10.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
10.000	0.000	tNET	RR	1	R2C2[3][B]	u_la0_top/capture_window_sel_10_s1/CLK
9.653	-0.347	tSu		1	R2C2[3][B]	u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.210, 90.489%; tC2Q: 0.442, 9.511%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.322
Data Arrival Time	2.264
Data Required Time	1.942
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_st/key_1_s0
To	u_pcie_ctrl/gtr12_pmac_inst
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.279	1.279	tNET	RR	1	R16C76[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_st/key_1_s0/CLK
1.459	0.180	tC2Q	RR	2	R16C76[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_st/key_1_s0/Q
2.264	0.805	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/FABRIC_TL_NPOR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.312	1.312	tNET	RR	1	R0C38	u_pcie_ctrl/gtr12_pmac_inst/TL_CLKP
1.942	0.630	tHld		1	R0C38	u_pcie_ctrl/gtr12_pmac_inst

Path Statistics:

Clock Skew	0.033
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.279, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 81.726%; tC2Q: 0.180, 18.274%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.312, 100.000%

Path2

Path Summary:

Slack	0.514
Data Arrival Time	1.629
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_addr_l_r_0_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.629	0.155	tNET	RR	1	R43C69[0][B]	u_tlp_dec/rx_tlp_addr_l_r_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C69[0][B]	u_tlp_dec/rx_tlp_addr_l_r_0_s0/CLK
1.115	-0.189	tHld		1	R43C69[0][B]	u_tlp_dec/rx_tlp_addr_l_r_0_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.155, 46.269%; tC2Q: 0.180, 53.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path3

Path Summary:

Slack	0.514
Data Arrival Time	1.629
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_addr_l_r_4_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.629	0.155	tNET	RR	1	R43C69[0][A]	u_tlp_dec/rx_tlp_addr_l_r_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C69[0][A]	u_tlp_dec/rx_tlp_addr_l_r_4_s0/CLK
1.115	-0.189	tHld		1	R43C69[0][A]	u_tlp_dec/rx_tlp_addr_l_r_4_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.155, 46.269%; tC2Q: 0.180, 53.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path4

Path Summary:

Slack	0.514
Data Arrival Time	1.629
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_hdr_2_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.629	0.155	tNET	RR	1	R43C69[1][B]	u_tlp_dec/rx_tlp_hdr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C69[1][B]	u_tlp_dec/rx_tlp_hdr_2_s0/CLK
1.115	-0.189	tHld		1	R43C69[1][B]	u_tlp_dec/rx_tlp_hdr_2_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.155, 46.269%; tC2Q: 0.180, 53.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path5

Path Summary:

Slack	0.514
Data Arrival Time	1.629
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_hdr_6_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.629	0.155	tNET	RR	1	R43C69[2][A]	u_tlp_dec/rx_tlp_hdr_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C69[2][A]	u_tlp_dec/rx_tlp_hdr_6_s0/CLK
1.115	-0.189	tHld		1	R43C69[2][A]	u_tlp_dec/rx_tlp_hdr_6_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.155, 46.269%; tC2Q: 0.180, 53.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path6

Path Summary:

Slack	0.514
Data Arrival Time	1.629
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_hdr_34_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.629	0.155	tNET	RR	1	R43C69[2][B]	u_tlp_dec/rx_tlp_hdr_34_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C69[2][B]	u_tlp_dec/rx_tlp_hdr_34_s0/CLK
1.115	-0.189	tHld		1	R43C69[2][B]	u_tlp_dec/rx_tlp_hdr_34_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.155, 46.269%; tC2Q: 0.180, 53.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path7

Path Summary:

Slack	0.519
Data Arrival Time	1.634
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_cmd_if/addrb_6_s4
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.634	0.160	tNET	RR	1	R43C73[0][A]	u_cmd_if/addrb_6_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C73[0][A]	u_cmd_if/addrb_6_s4/CLK
1.115	-0.189	tHld		1	R43C73[0][A]	u_cmd_if/addrb_6_s4

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.160, 47.059%; tC2Q: 0.180, 52.941%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path8

Path Summary:

Slack	0.519
Data Arrival Time	1.634
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_cmd_if/addrb_7_s4
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.634	0.160	tNET	RR	1	R43C73[0][B]	u_cmd_if/addrb_7_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C73[0][B]	u_cmd_if/addrb_7_s4/CLK
1.115	-0.189	tHld		1	R43C73[0][B]	u_cmd_if/addrb_7_s4

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.160, 47.059%; tC2Q: 0.180, 52.941%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path9

Path Summary:

Slack	0.519
Data Arrival Time	1.634
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_cmd_if/addrb_8_s4
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.634	0.160	tNET	RR	1	R43C73[1][B]	u_cmd_if/addrb_8_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C73[1][B]	u_cmd_if/addrb_8_s4/CLK
1.115	-0.189	tHld		1	R43C73[1][B]	u_cmd_if/addrb_8_s4

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.160, 47.059%; tC2Q: 0.180, 52.941%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path10

Path Summary:

Slack	0.519
Data Arrival Time	1.634
Data Required Time	1.115
From	pcie_st_cnt_8_s0
To	u_cmd_if/fsm_1_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.634	0.160	tNET	RR	1	R43C73[1][A]	u_cmd_if/fsm_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.304	1.304	tNET	RR	1	R43C73[1][A]	u_cmd_if/fsm_1_s0/CLK
1.115	-0.189	tHld		1	R43C73[1][A]	u_cmd_if/fsm_1_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.160, 47.059%; tC2Q: 0.180, 52.941%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.304, 100.000%

Path11

Path Summary:

Slack	0.528
Data Arrival Time	1.651
Data Required Time	1.124
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_req_id_r_2_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.651	0.178	tNET	RR	1	R39C69[0][B]	u_tlp_dec/rx_tlp_req_id_r_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.312	1.312	tNET	RR	1	R39C69[0][B]	u_tlp_dec/rx_tlp_req_id_r_2_s0/CLK
1.124	-0.189	tHld		1	R39C69[0][B]	u_tlp_dec/rx_tlp_req_id_r_2_s0

Path Statistics:

Clock Skew	0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.178, 49.650%; tC2Q: 0.180, 50.350%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.312, 100.000%

Path12

Path Summary:

Slack	0.530
Data Arrival Time	1.649
Data Required Time	1.119
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_cmd_en_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.649	0.175	tNET	RR	1	R39C72[0][B]	u_tlp_dec/rx_tlp_cmd_en_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.307	1.307	tNET	RR	1	R39C72[0][B]	u_tlp_dec/rx_tlp_cmd_en_s0/CLK
1.119	-0.189	tHld		1	R39C72[0][B]	u_tlp_dec/rx_tlp_cmd_en_s0

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 49.296%; tC2Q: 0.180, 50.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.307, 100.000%

Path13

Path Summary:

Slack	0.530
Data Arrival Time	1.649
Data Required Time	1.119
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_sop_r_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.649	0.175	tNET	RR	1	R39C72[0][A]	u_tlp_dec/rx_sop_r_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.307	1.307	tNET	RR	1	R39C72[0][A]	u_tlp_dec/rx_sop_r_s0/CLK
1.119	-0.189	tHld		1	R39C72[0][A]	u_tlp_dec/rx_sop_r_s0

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 49.296%; tC2Q: 0.180, 50.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.307, 100.000%

Path14

Path Summary:

Slack	0.596
Data Arrival Time	1.690
Data Required Time	1.093
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_1_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.690	0.232	tNET	RR	1	R36C72[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.282	1.282	tNET	RR	1	R36C72[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
1.093	-0.189	tHld		1	R36C72[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_1_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.232, 56.364%; tC2Q: 0.180, 43.636%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.282, 100.000%

Path15

Path Summary:

Slack	0.596
Data Arrival Time	1.690
Data Required Time	1.093
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_2_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.690	0.232	tNET	RR	1	R36C72[2][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.282	1.282	tNET	RR	1	R36C72[2][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_2_s1/CLK
1.093	-0.189	tHld		1	R36C72[2][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_2_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.232, 56.364%; tC2Q: 0.180, 43.636%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.282, 100.000%

Path16

Path Summary:

Slack	0.596
Data Arrival Time	1.690
Data Required Time	1.093
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_3_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.690	0.232	tNET	RR	1	R36C72[0][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.282	1.282	tNET	RR	1	R36C72[0][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_3_s1/CLK
1.093	-0.189	tHld		1	R36C72[0][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_3_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.232, 56.364%; tC2Q: 0.180, 43.636%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.282, 100.000%

Path17

Path Summary:

Slack	0.599
Data Arrival Time	1.686
Data Required Time	1.087
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_7_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.686	0.229	tNET	RR	1	R35C71[1][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.276	1.276	tNET	RR	1	R35C71[1][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_7_s1/CLK
1.087	-0.189	tHld		1	R35C71[1][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_7_s1

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.229, 55.963%; tC2Q: 0.180, 44.037%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.276, 100.000%

Path18

Path Summary:

Slack	0.620
Data Arrival Time	1.712
Data Required Time	1.092
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_4_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.712	0.255	tNET	RR	1	R35C72[1][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.281	1.281	tNET	RR	1	R35C72[1][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_4_s1/CLK
1.092	-0.189	tHld		1	R35C72[1][B]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_4_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.255, 58.621%; tC2Q: 0.180, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.281, 100.000%

Path19

Path Summary:

Slack	0.620
Data Arrival Time	1.712
Data Required Time	1.092
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_5_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.712	0.255	tNET	RR	1	R35C72[1][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.281	1.281	tNET	RR	1	R35C72[1][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_5_s1/CLK
1.092	-0.189	tHld		1	R35C72[1][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_5_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.255, 58.621%; tC2Q: 0.180, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.281, 100.000%

Path20

Path Summary:

Slack	0.620
Data Arrival Time	1.712
Data Required Time	1.092
From	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0
To	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_6_s1
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.277	1.277	tNET	RR	1	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/CLK
1.457	0.180	tC2Q	RR	14	R36C71[2][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_rstn/key_1_s0/Q
1.712	0.255	tNET	RR	1	R35C72[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.281	1.281	tNET	RR	1	R35C72[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_6_s1/CLK
1.092	-0.189	tHld		1	R35C72[0][A]	u_pcie_ctrl/PCIE_Controller_Top_inst/u_pcie_controller/u_pcie_linkup/cnt_6_s1

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.277, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.255, 58.621%; tC2Q: 0.180, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.281, 100.000%

Path21

Path Summary:

Slack	0.627
Data Arrival Time	1.741
Data Required Time	1.114
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_hdr_3_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.741	0.267	tNET	RR	1	R41C70[0][A]	u_tlp_dec/rx_tlp_hdr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.303	1.303	tNET	RR	1	R41C70[0][A]	u_tlp_dec/rx_tlp_hdr_3_s0/CLK
1.114	-0.189	tHld		1	R41C70[0][A]	u_tlp_dec/rx_tlp_hdr_3_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.267, 59.777%; tC2Q: 0.180, 40.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.303, 100.000%

Path22

Path Summary:

Slack	0.627
Data Arrival Time	1.741
Data Required Time	1.114
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_hdr_4_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.741	0.267	tNET	RR	1	R41C70[0][B]	u_tlp_dec/rx_tlp_hdr_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.303	1.303	tNET	RR	1	R41C70[0][B]	u_tlp_dec/rx_tlp_hdr_4_s0/CLK
1.114	-0.189	tHld		1	R41C70[0][B]	u_tlp_dec/rx_tlp_hdr_4_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.267, 59.777%; tC2Q: 0.180, 40.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.303, 100.000%

Path23

Path Summary:

Slack	0.627
Data Arrival Time	1.741
Data Required Time	1.114
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_hdr_5_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.741	0.267	tNET	RR	1	R41C70[1][A]	u_tlp_dec/rx_tlp_hdr_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.303	1.303	tNET	RR	1	R41C70[1][A]	u_tlp_dec/rx_tlp_hdr_5_s0/CLK
1.114	-0.189	tHld		1	R41C70[1][A]	u_tlp_dec/rx_tlp_hdr_5_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.267, 59.777%; tC2Q: 0.180, 40.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.303, 100.000%

Path24

Path Summary:

Slack	0.629
Data Arrival Time	1.741
Data Required Time	1.112
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_addr_l_r_1_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.741	0.267	tNET	RR	1	R42C70[0][A]	u_tlp_dec/rx_tlp_addr_l_r_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.301	1.301	tNET	RR	1	R42C70[0][A]	u_tlp_dec/rx_tlp_addr_l_r_1_s0/CLK
1.112	-0.189	tHld		1	R42C70[0][A]	u_tlp_dec/rx_tlp_addr_l_r_1_s0

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.267, 59.777%; tC2Q: 0.180, 40.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.301, 100.000%

Path25

Path Summary:

Slack	0.629
Data Arrival Time	1.741
Data Required Time	1.112
From	pcie_st_cnt_8_s0
To	u_tlp_dec/rx_tlp_addr_l_r_2_s0
Launch Clk	div_clk:[R]
Latch Clk	div_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.294	1.294	tNET	RR	1	R43C71[0][B]	pcie_st_cnt_8_s0/CLK
1.474	0.180	tC2Q	RR	1563	R43C71[0][B]	pcie_st_cnt_8_s0/Q
1.741	0.267	tNET	RR	1	R42C70[0][B]	u_tlp_dec/rx_tlp_addr_l_r_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					div_clk
0.000	0.000	tCL	RR	6003	BOTTOMSIDE[6]	uut_div2/CLKOUT
1.301	1.301	tNET	RR	1	R42C70[0][B]	u_tlp_dec/rx_tlp_addr_l_r_2_s0/CLK
1.112	-0.189	tHld		1	R42C70[0][B]	u_tlp_dec/rx_tlp_addr_l_r_2_s0

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.267, 59.777%; tC2Q: 0.180, 40.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.301, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.620
Actual Width:	3.620
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.954	2.954	tNET	RR	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.574	1.574	tNET	FF	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKB

MPW2

MPW Summary:

Slack:	2.620
Actual Width:	3.620
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.954	2.954	tNET	RR	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.574	1.574	tNET	FF	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKB

MPW3

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKB

MPW4

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_3_s/CLKA

MPW5

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_4_s/CLKB

MPW6

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_5_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	chn_loop_i[0].u_tlp_cpld_dec/u_sdp_cpld/gen_bsram.Bram_gen_bsram.Bram_0_5_s/CLKB

MPW7

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	u_cc_ctrl/u_sdp_mem/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	u_cc_ctrl/u_sdp_mem/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	u_cc_ctrl/u_sdp_mem/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA

MPW8

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	u_tl_tx/u_tx_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_2_s/CLKA

MPW9

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	chn_loop_i[0].u_tlp_rq/u_cmd_queue/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_1_s/CLKA

MPW10

MPW Summary:

Slack:	2.625
Actual Width:	3.625
Required Width:	1.000
Type:	High Pulse Width
Clock:	div_clk
Objects:	chn_loop_i[0].u_tlp_rq/u_rq_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			div_clk
0.000	0.000	tCL	RR	uut_div2/CLKOUT
2.945	2.945	tNET	RR	chn_loop_i[0].u_tlp_rq/u_rq_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			div_clk
5.000	0.000	tCL	FF	uut_div2/CLKOUT
6.570	1.570	tNET	FF	chn_loop_i[0].u_tlp_rq/u_rq_buf/u_sdp/gen_bsram.Bram_gen_bsram.Bram_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
6003	cfg_clk	-1.914	3.058
1563	pcie_st_cnt[8]	-0.376	12.071
537	port_sel[1]	-1.629	6.499
496	tl_bardec[0]	3.144	4.278
496	tl_bardec[1]	2.061	5.626
496	tl_bardec[2]	2.493	4.858
270	port_sel[0]	0.699	5.024
266	cpl_sel[0]	1.516	7.523
266	cpl_sel[3]	-1.261	10.611
266	np_sel[3]	3.443	5.825

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R10C85	75.00%
R10C98	72.22%
R10C99	72.22%
R10C84	70.83%
R1C73	66.67%
R1C77	66.67%
R10C100	66.67%
R1C74	63.89%
R1C76	63.89%
R1C75	63.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name div_clk -period 10 -waveform {0 5} [get_pins {uut_div2/CLKOUT}]