Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SERDES_IP\IPlib\PCIE\data\pcie_controller_encrypt.v
H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SERDES_IP\IPlib\PCIE\data\pcie_controller_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Mon Sep 30 13:49:28 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PCIE_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 104.898MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 104.898MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 104.898MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 104.898MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 104.898MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 104.898MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 104.898MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 104.898MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 104.898MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 104.898MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 104.898MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 104.898MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 128.414MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 128.414MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 128.414MB
Total Time and Memory Usage CPU time = 0h 0m 0.403s, Elapsed time = 0h 0m 0.51s, Peak memory usage = 128.414MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 2125
I/O Buf 1428
    IBUF 673
    OBUF 755
Register 44
    DFFRE 18
    DFFPE 2
    DFFCE 24
LUT 20
    LUT2 8
    LUT3 2
    LUT4 10
ALU 14
    ALU 14
INV 3
    INV 3

Resource Utilization Summary

Resource Usage Utilization
Logic 37(23 LUT, 14 ALU) / 138240 <1%
Register 44 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 44 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
pcie_tl_clk_i Base 10.000 100.0 0.000 5.000 pcie_tl_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 pcie_tl_clk_i 100.000(MHz) 323.756(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.911
Data Arrival Time 3.872
Data Required Time 10.784
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_7_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.683 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
1.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
1.477 0.382 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
1.890 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
2.469 0.579 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
2.881 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s3/I0
3.460 0.579 tINS RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s3/F
3.872 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.682 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
11.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s1/CLK
10.784 -0.311 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 1.158, 41.674%; route: 1.238, 44.555%; tC2Q: 0.382, 13.771%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 2

Path Summary:
Slack 7.159
Data Arrival Time 3.872
Data Required Time 11.031
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_6_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.683 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
1.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
1.477 0.382 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
1.890 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
2.469 0.579 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
2.881 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/n27_s2/I0
3.460 0.579 tINS RR 1 u_pcie_controller/u_pcie_linkup/n27_s2/F
3.872 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.682 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
11.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_6_s1/CLK
11.031 -0.064 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 1.158, 41.674%; route: 1.238, 44.555%; tC2Q: 0.382, 13.771%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 3

Path Summary:
Slack 7.170
Data Arrival Time 3.861
Data Required Time 11.031
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_3_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.683 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
1.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
1.477 0.382 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
1.890 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/n31_s3/I0
2.469 0.579 tINS RR 1 u_pcie_controller/u_pcie_linkup/n31_s3/F
2.881 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/n30_s2/I1
3.449 0.567 tINS RR 1 u_pcie_controller/u_pcie_linkup/n30_s2/F
3.861 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.682 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
11.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_3_s1/CLK
11.031 -0.064 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 4

Path Summary:
Slack 7.170
Data Arrival Time 3.861
Data Required Time 11.031
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_4_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.683 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
1.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
1.477 0.382 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
1.890 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
2.469 0.579 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
2.881 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/n29_s3/I1
3.449 0.567 tINS RR 1 u_pcie_controller/u_pcie_linkup/n29_s3/F
3.861 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.682 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
11.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_4_s1/CLK
11.031 -0.064 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 5

Path Summary:
Slack 7.170
Data Arrival Time 3.861
Data Required Time 11.031
From u_pcie_controller/u_pcie_linkup/cnt_1_s1
To u_pcie_controller/u_pcie_linkup/cnt_5_s1
Launch Clk pcie_tl_clk_i[R]
Latch Clk pcie_tl_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pcie_tl_clk_i
0.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
0.683 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
1.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK
1.477 0.382 tC2Q RR 4 u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q
1.890 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0
2.469 0.579 tINS RR 4 u_pcie_controller/u_pcie_linkup/cnt_7_s4/F
2.881 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/n28_s2/I1
3.449 0.567 tINS RR 1 u_pcie_controller/u_pcie_linkup/n28_s2/F
3.861 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pcie_tl_clk_i
10.000 0.000 tCL RR 1 pcie_tl_clk_i_ibuf/I
10.682 0.683 tINS RR 44 pcie_tl_clk_i_ibuf/O
11.095 0.413 tNET RR 1 u_pcie_controller/u_pcie_linkup/cnt_5_s1/CLK
11.031 -0.064 tSu 1 u_pcie_controller/u_pcie_linkup/cnt_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%