# Reading D:/altera/13.0/modelsim_ae/tcl/vsim/pref.tcl 
# ERROR: No extended dataflow license exists
# do AC_I2C_Control_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\altera\13.0\modelsim_ae\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\altera\13.0\modelsim_ae\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj {F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_bit_shift.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_bit_shift
# 
# Top level modules:
# 	i2c_bit_shift
# vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj {F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control
# 
# Top level modules:
# 	i2c_control
# 
# vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj {F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control_tb
# 
# Top level modules:
# 	i2c_control_tb
# vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj {F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  i2c_control_tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps i2c_control_tb 
# //  ModelSim ALTERA 10.1d Nov  2 2012 
# //
# //  Copyright 1991-2012 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.i2c_control_tb
# Loading work.i2c_control
# Loading work.i2c_bit_shift
# Loading work.M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# 
# add wave *
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# 
#           File in use by: Administrator  Hostname: USER-20170329RI  ProcessID: 11604
# 
#           Attempting to use alternate WLF file "./wlfttxacqh".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# 
#           Using alternate file: ./wlfttxacqh
# 
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 78
# Simulation Breakpoint: Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 78
# MACRO ./AC_I2C_Control_run_msim_rtl_verilog.do PAUSED at line 19
add wave -position insertpoint sim:/i2c_control_tb/i2c_control/*
add wave -position insertpoint sim:/i2c_control_tb/i2c_control/i2c_bit_shift/*
add wave -position insertpoint sim:/i2c_control_tb/M24LC04B/*
restart
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 78
add wave -position insertpoint  \
sim:/i2c_control_tb/M24LC04B/A0 \
sim:/i2c_control_tb/M24LC04B/A1 \
sim:/i2c_control_tb/M24LC04B/A2 \
sim:/i2c_control_tb/M24LC04B/WP \
sim:/i2c_control_tb/M24LC04B/SDA \
sim:/i2c_control_tb/M24LC04B/SCL \
sim:/i2c_control_tb/M24LC04B/RESET \
sim:/i2c_control_tb/M24LC04B/SDA_DO \
sim:/i2c_control_tb/M24LC04B/SDA_OE \
sim:/i2c_control_tb/M24LC04B/SDA_DriveEnable \
sim:/i2c_control_tb/M24LC04B/SDA_DriveEnableDlyd \
sim:/i2c_control_tb/M24LC04B/BitCounter \
sim:/i2c_control_tb/M24LC04B/START_Rcvd \
sim:/i2c_control_tb/M24LC04B/STOP_Rcvd \
sim:/i2c_control_tb/M24LC04B/CTRL_Rcvd \
sim:/i2c_control_tb/M24LC04B/ADDR_Rcvd \
sim:/i2c_control_tb/M24LC04B/MACK_Rcvd \
sim:/i2c_control_tb/M24LC04B/WrCycle \
sim:/i2c_control_tb/M24LC04B/RdCycle \
sim:/i2c_control_tb/M24LC04B/ShiftRegister \
sim:/i2c_control_tb/M24LC04B/ControlByte \
sim:/i2c_control_tb/M24LC04B/BlockSelect \
sim:/i2c_control_tb/M24LC04B/RdWrBit \
sim:/i2c_control_tb/M24LC04B/StartAddress \
sim:/i2c_control_tb/M24LC04B/PageAddress \
sim:/i2c_control_tb/M24LC04B/WrDataByte \
sim:/i2c_control_tb/M24LC04B/RdDataByte \
sim:/i2c_control_tb/M24LC04B/WrCounter \
sim:/i2c_control_tb/M24LC04B/WrPointer \
sim:/i2c_control_tb/M24LC04B/RdPointer \
sim:/i2c_control_tb/M24LC04B/WriteActive \
sim:/i2c_control_tb/M24LC04B/MemoryBlock0 \
sim:/i2c_control_tb/M24LC04B/MemoryBlock1 \
sim:/i2c_control_tb/M24LC04B/LoopIndex \
sim:/i2c_control_tb/M24LC04B/tAA \
sim:/i2c_control_tb/M24LC04B/tWC \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_00 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_01 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_02 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_03 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_04 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_05 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_06 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_07 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_08 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_09 \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_0A \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_0B \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_0C \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_0D \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_0E \
sim:/i2c_control_tb/M24LC04B/MemoryByte0_0F \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_00 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_01 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_02 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_03 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_04 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_05 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_06 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_07 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_08 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_09 \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_0A \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_0B \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_0C \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_0D \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_0E \
sim:/i2c_control_tb/M24LC04B/MemoryByte1_0F \
sim:/i2c_control_tb/M24LC04B/WriteData_0 \
sim:/i2c_control_tb/M24LC04B/WriteData_1 \
sim:/i2c_control_tb/M24LC04B/WriteData_2 \
sim:/i2c_control_tb/M24LC04B/WriteData_3 \
sim:/i2c_control_tb/M24LC04B/WriteData_4 \
sim:/i2c_control_tb/M24LC04B/WriteData_5 \
sim:/i2c_control_tb/M24LC04B/WriteData_6 \
sim:/i2c_control_tb/M24LC04B/WriteData_7 \
sim:/i2c_control_tb/M24LC04B/WriteData_8 \
sim:/i2c_control_tb/M24LC04B/WriteData_9 \
sim:/i2c_control_tb/M24LC04B/WriteData_A \
sim:/i2c_control_tb/M24LC04B/WriteData_B \
sim:/i2c_control_tb/M24LC04B/WriteData_C \
sim:/i2c_control_tb/M24LC04B/WriteData_D \
sim:/i2c_control_tb/M24LC04B/WriteData_E \
sim:/i2c_control_tb/M24LC04B/WriteData_F \
sim:/i2c_control_tb/M24LC04B/TimingCheckEnable
restart
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 78
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_bit_shift.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_bit_shift
# 
# Top level modules:
# 	i2c_bit_shift
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control
# 
# Top level modules:
# 	i2c_control
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control_tb
# 
# Top level modules:
# 	i2c_control_tb
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
restart
# Loading work.i2c_control_tb
# Loading work.i2c_control
# Loading work.i2c_bit_shift
# Loading work.M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 78
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_bit_shift.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_bit_shift
# 
# Top level modules:
# 	i2c_bit_shift
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control
# 
# Top level modules:
# 	i2c_control
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control_tb
# 
# Top level modules:
# 	i2c_control_tb
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
restart
# Loading work.i2c_control_tb
# Loading work.i2c_control
# Loading work.i2c_bit_shift
# Loading work.M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 78
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_bit_shift.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_bit_shift
# 
# Top level modules:
# 	i2c_bit_shift
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control
# 
# Top level modules:
# 	i2c_control
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control_tb
# 
# Top level modules:
# 	i2c_control_tb
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
restart
# Loading work.i2c_control_tb
# Loading work.i2c_control
# Loading work.i2c_bit_shift
# Loading work.M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 80
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_bit_shift.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_bit_shift
# 
# Top level modules:
# 	i2c_bit_shift
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control
# 
# Top level modules:
# 	i2c_control
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control_tb
# 
# Top level modules:
# 	i2c_control_tb
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
restart
# Loading work.i2c_control_tb
# Loading work.i2c_control
# Loading work.i2c_bit_shift
# Loading work.M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 80
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_bit_shift.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_bit_shift
# 
# Top level modules:
# 	i2c_bit_shift
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control
# 
# Top level modules:
# 	i2c_control
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module i2c_control_tb
# 
# Top level modules:
# 	i2c_control_tb
vlog -vlog01compat -work work +incdir+F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj -O0 F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module M24LC04B
# 
# Top level modules:
# 	M24LC04B
restart
# Loading work.i2c_control_tb
# Loading work.i2c_control
# Loading work.i2c_bit_shift
# Loading work.M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A0'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A1'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'A2'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
# ** Warning: (vsim-3015) F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v(46): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'WP'. The port definition is at: F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/M24LC04B.v(85).
# 
#         Region: /i2c_control_tb/M24LC04B
run -all
# Break in Module i2c_control_tb at F:/FPGA/Firmware/01_Project/Verilog/Debug/AC_I2C_Control/prj/i2c_control_tb.v line 80
