Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\src\uart_byte_rx.v
H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\src\uart_byte_tx.v
H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\src\uart_data_rx.v
H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\src\uart_data_tx.v
H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\src\uart_loopback.v
H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
H:\0_gaoyun_p\1.9.9Beta_6\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\gw_jtag.v
H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Mon Apr 15 13:38:45 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module uart_loopback
Synthesis Process Running parser:
    CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.425s, Peak memory usage = 82.168MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 82.168MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 82.168MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 82.168MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 82.168MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 82.168MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 82.168MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 82.168MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 82.168MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 82.168MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 82.168MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 96.391MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 96.391MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 96.391MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 96.391MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 11
I/O Buf 11
    IBUF 6
    OBUF 5
Register 571
    DFFRE 34
    DFFPE 38
    DFFCE 499
LUT 605
    LUT2 82
    LUT3 182
    LUT4 341
MUX 1
    MUX16 1
ALU 10
    ALU 10
INV 5
    INV 5
BSRAM 4
    SDPX9B 4
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 628(618 LUT, 10 ALU) / 23040 3%
Register 571 / 23685 3%
  --Register as Latch 0 / 23685 0%
  --Register as FF 571 / 23685 3%
BSRAM 4 / 56 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
Clk Base 10.000 100.0 0.000 5.000 Clk_ibuf/I
gw_gao_inst_0/u_icon_top/n19_6 Base 10.000 100.0 0.000 5.000 gw_gao_inst_0/u_icon_top/n19_s2/O
gw_gao_inst_0/u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 gw_gao_inst_0/u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 Clk 100.0(MHz) 221.6(MHz) 7 TOP
2 gw_gao_inst_0/u_icon_top/n19_6 100.0(MHz) 1577.9(MHz) 1 TOP
3 gw_gao_inst_0/u_la0_top/n15_6 100.0(MHz) 1577.9(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.488
Data Arrival Time 5.319
Data Required Time 10.806
From uart_data_rx/timeout_cnt_2_s0
To uart_data_rx/timeout_cnt_12_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.683 0.683 tINS RR 334 Clk_ibuf/O
0.870 0.188 tNET RR 1 uart_data_rx/timeout_cnt_2_s0/CLK
1.253 0.382 tC2Q RR 4 uart_data_rx/timeout_cnt_2_s0/Q
1.440 0.188 tNET RR 1 uart_data_rx/n191_s3/I0
1.966 0.526 tINS RR 3 uart_data_rx/n191_s3/F
2.154 0.188 tNET RR 1 uart_data_rx/n189_s3/I2
2.615 0.461 tINS RR 3 uart_data_rx/n189_s3/F
2.803 0.188 tNET RR 1 uart_data_rx/n187_s3/I2
3.264 0.461 tINS RR 4 uart_data_rx/n187_s3/F
3.451 0.188 tNET RR 1 uart_data_rx/n184_s3/I3
3.714 0.262 tINS RR 3 uart_data_rx/n184_s3/F
3.901 0.188 tNET RR 1 uart_data_rx/n183_s3/I1
4.418 0.516 tINS RR 1 uart_data_rx/n183_s3/F
4.605 0.188 tNET RR 1 uart_data_rx/n183_s2/I0
5.131 0.526 tINS RR 1 uart_data_rx/n183_s2/F
5.319 0.188 tNET RR 1 uart_data_rx/timeout_cnt_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.682 0.683 tINS RR 334 Clk_ibuf/O
10.870 0.188 tNET RR 1 uart_data_rx/timeout_cnt_12_s0/CLK
10.806 -0.064 tSu 1 uart_data_rx/timeout_cnt_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.754, 61.899%; route: 1.313, 29.503%; tC2Q: 0.382, 8.598%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 2

Path Summary:
Slack 5.542
Data Arrival Time 5.264
Data Required Time 10.806
From uart_data_rx/timeout_cnt_2_s0
To uart_data_rx/timeout_cnt_13_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.683 0.683 tINS RR 334 Clk_ibuf/O
0.870 0.188 tNET RR 1 uart_data_rx/timeout_cnt_2_s0/CLK
1.253 0.382 tC2Q RR 4 uart_data_rx/timeout_cnt_2_s0/Q
1.440 0.188 tNET RR 1 uart_data_rx/n191_s3/I0
1.966 0.526 tINS RR 3 uart_data_rx/n191_s3/F
2.154 0.188 tNET RR 1 uart_data_rx/n189_s3/I2
2.615 0.461 tINS RR 3 uart_data_rx/n189_s3/F
2.803 0.188 tNET RR 1 uart_data_rx/n187_s3/I2
3.264 0.461 tINS RR 4 uart_data_rx/n187_s3/F
3.451 0.188 tNET RR 1 uart_data_rx/n184_s3/I3
3.714 0.262 tINS RR 3 uart_data_rx/n184_s3/F
3.901 0.188 tNET RR 1 uart_data_rx/n182_s3/I2
4.363 0.461 tINS RR 1 uart_data_rx/n182_s3/F
4.550 0.188 tNET RR 1 uart_data_rx/n182_s2/I0
5.076 0.526 tINS RR 1 uart_data_rx/n182_s2/F
5.264 0.188 tNET RR 1 uart_data_rx/timeout_cnt_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.682 0.683 tINS RR 334 Clk_ibuf/O
10.870 0.188 tNET RR 1 uart_data_rx/timeout_cnt_13_s0/CLK
10.806 -0.064 tSu 1 uart_data_rx/timeout_cnt_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.699, 61.422%; route: 1.313, 29.872%; tC2Q: 0.382, 8.706%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 3

Path Summary:
Slack 5.937
Data Arrival Time 4.869
Data Required Time 10.806
From uart_data_rx/timeout_cnt_2_s0
To uart_data_rx/timeout_cnt_9_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.683 0.683 tINS RR 334 Clk_ibuf/O
0.870 0.188 tNET RR 1 uart_data_rx/timeout_cnt_2_s0/CLK
1.253 0.382 tC2Q RR 4 uart_data_rx/timeout_cnt_2_s0/Q
1.440 0.188 tNET RR 1 uart_data_rx/n191_s3/I0
1.966 0.526 tINS RR 3 uart_data_rx/n191_s3/F
2.154 0.188 tNET RR 1 uart_data_rx/n189_s3/I2
2.615 0.461 tINS RR 3 uart_data_rx/n189_s3/F
2.803 0.188 tNET RR 1 uart_data_rx/n187_s3/I2
3.264 0.461 tINS RR 4 uart_data_rx/n187_s3/F
3.451 0.188 tNET RR 1 uart_data_rx/n186_s3/I1
3.968 0.516 tINS RR 1 uart_data_rx/n186_s3/F
4.155 0.188 tNET RR 1 uart_data_rx/n186_s2/I0
4.681 0.526 tINS RR 1 uart_data_rx/n186_s2/F
4.869 0.188 tNET RR 1 uart_data_rx/timeout_cnt_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.682 0.683 tINS RR 334 Clk_ibuf/O
10.870 0.188 tNET RR 1 uart_data_rx/timeout_cnt_9_s0/CLK
10.806 -0.064 tSu 1 uart_data_rx/timeout_cnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.491, 62.301%; route: 1.125, 28.134%; tC2Q: 0.382, 9.565%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 4

Path Summary:
Slack 6.136
Data Arrival Time 4.670
Data Required Time 10.806
From uart_data_tx/uart_byte_tx/div_cnt_9_s0
To uart_data_tx/uart_byte_tx/div_cnt_1_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.683 0.683 tINS RR 334 Clk_ibuf/O
0.870 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/div_cnt_9_s0/CLK
1.253 0.382 tC2Q RR 6 uart_data_tx/uart_byte_tx/div_cnt_9_s0/Q
1.440 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n154_s5/I0
1.966 0.526 tINS RR 1 uart_data_tx/uart_byte_tx/n154_s5/F
2.154 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n154_s2/I3
2.416 0.262 tINS RR 2 uart_data_tx/uart_byte_tx/n154_s2/F
2.604 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n131_s4/I1
3.120 0.516 tINS RR 1 uart_data_tx/uart_byte_tx/n131_s4/F
3.307 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n131_s3/I0
3.834 0.526 tINS RR 13 uart_data_tx/uart_byte_tx/n131_s3/F
4.021 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n131_s2/I2
4.482 0.461 tINS RR 1 uart_data_tx/uart_byte_tx/n131_s2/F
4.670 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/div_cnt_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.682 0.683 tINS RR 334 Clk_ibuf/O
10.870 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/div_cnt_1_s0/CLK
10.806 -0.064 tSu 1 uart_data_tx/uart_byte_tx/div_cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%

Path 5

Path Summary:
Slack 6.136
Data Arrival Time 4.670
Data Required Time 10.806
From uart_data_tx/uart_byte_tx/div_cnt_9_s0
To uart_data_tx/uart_byte_tx/div_cnt_3_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.683 0.683 tINS RR 334 Clk_ibuf/O
0.870 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/div_cnt_9_s0/CLK
1.253 0.382 tC2Q RR 6 uart_data_tx/uart_byte_tx/div_cnt_9_s0/Q
1.440 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n154_s5/I0
1.966 0.526 tINS RR 1 uart_data_tx/uart_byte_tx/n154_s5/F
2.154 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n154_s2/I3
2.416 0.262 tINS RR 2 uart_data_tx/uart_byte_tx/n154_s2/F
2.604 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n131_s4/I1
3.120 0.516 tINS RR 1 uart_data_tx/uart_byte_tx/n131_s4/F
3.307 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n131_s3/I0
3.834 0.526 tINS RR 13 uart_data_tx/uart_byte_tx/n131_s3/F
4.021 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/n129_s2/I2
4.482 0.461 tINS RR 1 uart_data_tx/uart_byte_tx/n129_s2/F
4.670 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/div_cnt_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.682 0.683 tINS RR 334 Clk_ibuf/O
10.870 0.188 tNET RR 1 uart_data_tx/uart_byte_tx/div_cnt_3_s0/CLK
10.806 -0.064 tSu 1 uart_data_tx/uart_byte_tx/div_cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: cell: 2.293, 60.329%; route: 1.125, 29.605%; tC2Q: 0.382, 10.066%
Required Clock Path Delay: cell: 0.683, 78.448%; route: 0.188, 21.552%