Timing Messages

Report Title	Timing Analysis Report
Design File	H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\impl\gwsynthesis\uart_loopback.vg
Physical Constraints File	H:\01_gaoyun\01_gao_project\09_uart_loopback\uart_loopback\src\uart_loopback.cst
Timing Constraint File	---
Version	V1.9.9 Beta-6
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Mon Apr 15 13:38:50 2024
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.85V -40C ES
Hold Delay Model	Fast 0.95V 100C ES
Numbers of Paths Analyzed	1452
Numbers of Endpoints Analyzed	1882
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	1

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
Clk	Base	10.000	100.000	0.000	5.000			Clk_ibuf/I
tck_pad_i	Base	50.000	20.000	0.000	25.000			gw_gao_inst_0/tck_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	100.000(MHz)	189.798(MHz)	3	TOP
2	tck_pad_i	20.000(MHz)	107.817(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
Clk	Setup	0.000	0
Clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.702	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	Clk:[R]	10.000	2.171	4.781
2	2.923	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	Clk:[R]	10.000	2.158	4.573
3	3.093	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.144	4.665
4	3.156	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.173	4.573
5	3.156	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.173	4.573
6	3.226	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	Clk:[R]	10.000	2.148	4.280
7	3.266	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.151	4.485
8	3.331	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.151	4.420
9	3.359	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	Clk:[R]	10.000	2.151	4.144
10	3.411	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.151	4.340
11	3.423	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.136	4.343
12	3.528	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.136	4.244
13	3.549	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.136	4.216
14	3.578	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.182	4.141
15	3.675	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.136	4.090
16	3.675	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.136	4.090
17	3.675	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.136	4.090
18	3.698	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.158	4.045
19	4.114	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D	tck_pad_i:[R]	Clk:[R]	10.000	2.163	3.624
20	4.180	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/D	tck_pad_i:[R]	Clk:[R]	10.000	2.161	3.560
21	4.349	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.146	3.406
22	4.726	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/D	tck_pad_i:[R]	Clk:[R]	10.000	2.142	3.034
23	4.731	uart_data_tx/cnt_6_s1/Q	uart_data_tx/Tx_Done_s0/D	Clk:[R]	Clk:[R]	10.000	-0.043	5.247
24	4.869	uart_data_tx/state_1_s0/Q	uart_data_tx/Tx_Done_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.031	4.851
25	4.873	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D	tck_pad_i:[R]	Clk:[R]	10.000	2.134	2.894

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.020	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D	Clk:[R]	tck_pad_i:[R]	0.000	-1.545	0.561
2	0.068	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5]	Clk:[R]	Clk:[R]	0.000	0.011	0.306
3	0.083	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]	Clk:[R]	Clk:[R]	0.000	0.026	0.306
4	0.088	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5]	Clk:[R]	Clk:[R]	0.000	0.031	0.306
5	0.133	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]	Clk:[R]	Clk:[R]	0.000	0.023	0.359
6	0.133	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]	Clk:[R]	Clk:[R]	0.000	0.023	0.359
7	0.186	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[5]	Clk:[R]	Clk:[R]	0.000	0.019	0.416
8	0.196	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]	Clk:[R]	Clk:[R]	0.000	0.021	0.424
9	0.196	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]	Clk:[R]	Clk:[R]	0.000	0.021	0.424
10	0.196	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]	Clk:[R]	Clk:[R]	0.000	0.021	0.424
11	0.196	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	Clk:[R]	Clk:[R]	0.000	0.021	0.424
12	0.196	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]	Clk:[R]	Clk:[R]	0.000	0.021	0.424
13	0.203	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]	Clk:[R]	Clk:[R]	0.000	0.033	0.419
14	0.218	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/ADA[11]	Clk:[R]	Clk:[R]	0.000	0.016	0.320
15	0.218	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/ADA[6]	Clk:[R]	Clk:[R]	0.000	0.016	0.320
16	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[11]	Clk:[R]	Clk:[R]	0.000	0.021	0.322
17	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[6]	Clk:[R]	Clk:[R]	0.000	0.021	0.322
18	0.289	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]	Clk:[R]	Clk:[R]	0.000	0.021	0.517
19	0.289	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]	Clk:[R]	Clk:[R]	0.000	0.021	0.517
20	0.289	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]	Clk:[R]	Clk:[R]	0.000	0.021	0.517
21	0.293	gw_gao_inst_0/u_la0_top/triger_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[8]	Clk:[R]	Clk:[R]	0.000	0.002	0.540
22	0.308	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1]	Clk:[R]	Clk:[R]	0.000	0.018	0.539
23	0.308	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0]	Clk:[R]	Clk:[R]	0.000	0.018	0.539
24	0.310	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6]	Clk:[R]	Clk:[R]	0.000	0.023	0.536
25	0.313	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]	Clk:[R]	Clk:[R]	0.000	0.023	0.539

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.434	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.005	1.224
2	3.479	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.022	1.196
3	3.479	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.022	1.196
4	3.479	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.022	1.196
5	3.479	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.022	1.196
6	3.481	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.024	1.196
7	3.486	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.031	1.198
8	3.486	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.031	1.198
9	3.488	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.034	1.198
10	3.488	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.034	1.198
11	3.488	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.034	1.198
12	3.488	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.034	1.198
13	3.592	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.007	1.067
14	3.599	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	0.014	1.040
15	3.609	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.032	1.075
16	3.619	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.041	1.075
17	3.619	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.041	1.075
18	3.690	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	Clk:[F]	Clk:[R]	5.000	-0.010	0.973
19	3.690	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.010	0.973
20	3.690	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.010	0.973
21	3.694	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.027	0.986
22	3.694	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.027	0.986
23	3.694	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	Clk:[F]	Clk:[R]	5.000	-0.027	0.986
24	3.699	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.019	0.973
25	3.699	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	Clk:[F]	Clk:[R]	5.000	-0.019	0.973

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.201	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR	Clk:[F]	tck_pad_i:[R]	-5.000	-1.538	0.586
2	4.208	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR	Clk:[F]	tck_pad_i:[R]	-5.000	-1.537	0.591
3	4.328	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR	Clk:[F]	tck_pad_i:[R]	-5.000	-1.532	0.706
4	5.646	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.003	0.454
5	5.646	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.003	0.454
6	5.656	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.008	0.459
7	5.656	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.008	0.459
8	5.667	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.007	0.471
9	5.667	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.007	0.471
10	5.667	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.007	0.471
11	5.667	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.007	0.471
12	5.672	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.012	0.471
13	5.672	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.012	0.471
14	5.672	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.012	0.471
15	5.672	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.012	0.471
16	5.672	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.012	0.471
17	5.672	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	Clk:[F]	Clk:[R]	-5.000	0.012	0.471
18	5.719	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.015	0.545
19	5.719	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.015	0.545
20	5.723	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.021	0.556
21	5.723	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.021	0.556
22	5.723	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.021	0.556
23	5.723	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.021	0.556
24	5.723	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.021	0.556
25	5.723	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	Clk:[F]	Clk:[R]	-5.000	-0.021	0.556

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.486	4.486	1.000	Low Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
2	3.490	4.490	1.000	Low Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
3	3.490	4.490	1.000	Low Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
4	3.495	4.495	1.000	Low Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
5	3.497	4.497	1.000	High Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
6	3.502	4.502	1.000	High Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
7	3.502	4.502	1.000	High Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
8	3.506	4.506	1.000	High Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
9	4.230	4.480	0.250	Low Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
10	4.230	4.480	0.250	Low Pulse Width	Clk	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.702
Data Arrival Time	8.506
Data Required Time	11.208
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.724	2.359	tNET	RR	1	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.107	0.382	tC2Q	RR	2	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.763	1.656	tNET	RR	2	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/I1
6.326	0.563	tINS	RF	1	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/COUT
6.326	0.000	tNET	FF	2	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/CIN
6.376	0.050	tINS	FR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/COUT
6.376	0.000	tNET	RR	2	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/CIN
6.426	0.050	tINS	RR	5	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/COUT
7.022	0.596	tNET	RR	1	R18C52[3][A]	gw_gao_inst_0/u_la0_top/n1904_s1/I0
7.312	0.290	tINS	RF	1	R18C52[3][A]	gw_gao_inst_0/u_la0_top/n1904_s1/F
7.317	0.005	tNET	FF	1	R18C52[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
7.778	0.461	tINS	FR	1	R18C52[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
8.506	0.728	tNET	RR	1	R18C52[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.554	0.871	tNET	RR	1	R18C52[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
11.519	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
11.208	-0.311	tSu		1	R18C52[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-2.171
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.650%; route: 2.359, 63.350%
Arrival Data Path Delay	cell: 1.414, 29.569%; route: 2.985, 62.431%; tC2Q: 0.382, 8.000%
Required Clock Path Delay	cell: 0.683, 43.926%; route: 0.871, 56.074%

Path2

Path Summary:

Slack	2.923
Data Arrival Time	8.306
Data Required Time	11.229
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.734	2.369	tNET	RR	1	R20C46[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/CLK
4.116	0.382	tC2Q	RR	3	R20C46[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q
5.005	0.889	tNET	RR	1	R21C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I3
5.531	0.526	tINS	RR	1	R21C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
5.669	0.137	tNET	RR	1	R21C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
6.195	0.526	tINS	RR	3	R21C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
7.117	0.922	tNET	RR	1	R25C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
7.579	0.461	tINS	RR	1	R25C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
8.306	0.728	tNET	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.576	0.893	tNET	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
11.541	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
11.229	-0.311	tSu		1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-2.158
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.558%; route: 2.369, 63.442%
Arrival Data Path Delay	cell: 1.514, 33.106%; route: 2.676, 58.529%; tC2Q: 0.382, 8.365%
Required Clock Path Delay	cell: 0.683, 43.316%; route: 0.893, 56.684%

Path3

Path Summary:

Slack	3.093
Data Arrival Time	8.394
Data Required Time	11.486
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.877	0.687	tNET	RR	1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s2/I2
8.394	0.516	tINS	RR	1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s2/F
8.394	0.000	tNET	RR	1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.585	0.902	tNET	RR	1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
11.550	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
11.486	-0.064	tSu		1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	-2.144
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.811, 38.826%; route: 2.471, 52.974%; tC2Q: 0.382, 8.199%
Required Clock Path Delay	cell: 0.683, 43.060%; route: 0.902, 56.940%

Path4

Path Summary:

Slack	3.156
Data Arrival Time	8.297
Data Required Time	11.453
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.724	2.359	tNET	RR	1	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.107	0.382	tC2Q	RR	2	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.763	1.656	tNET	RR	2	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/I1
6.326	0.563	tINS	RF	1	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/COUT
6.326	0.000	tNET	FF	2	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/CIN
6.376	0.050	tINS	FR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/COUT
6.376	0.000	tNET	RR	2	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/CIN
6.426	0.050	tINS	RR	5	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/COUT
7.214	0.789	tNET	RR	1	R17C51[1][B]	gw_gao_inst_0/u_la0_top/n1885_s2/I1
7.676	0.461	tINS	RR	2	R17C51[1][B]	gw_gao_inst_0/u_la0_top/n1885_s2/F
7.836	0.160	tNET	RR	1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/n1883_s3/I3
8.297	0.461	tINS	RR	1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/n1883_s3/F
8.297	0.000	tNET	RR	1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.552	0.869	tNET	RR	1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
11.517	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
11.453	-0.064	tSu		1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-2.173
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.650%; route: 2.359, 63.350%
Arrival Data Path Delay	cell: 1.585, 34.664%; route: 2.605, 56.971%; tC2Q: 0.382, 8.365%
Required Clock Path Delay	cell: 0.683, 43.979%; route: 0.869, 56.021%

Path5

Path Summary:

Slack	3.156
Data Arrival Time	8.297
Data Required Time	11.453
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.724	2.359	tNET	RR	1	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.107	0.382	tC2Q	RR	2	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.763	1.656	tNET	RR	2	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/I1
6.326	0.563	tINS	RF	1	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/COUT
6.326	0.000	tNET	FF	2	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/CIN
6.376	0.050	tINS	FR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/COUT
6.376	0.000	tNET	RR	2	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/CIN
6.426	0.050	tINS	RR	5	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/COUT
7.214	0.789	tNET	RR	1	R17C51[1][B]	gw_gao_inst_0/u_la0_top/n1885_s2/I1
7.676	0.461	tINS	RR	2	R17C51[1][B]	gw_gao_inst_0/u_la0_top/n1885_s2/F
7.836	0.160	tNET	RR	1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/n1882_s1/I3
8.297	0.461	tINS	RR	1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/n1882_s1/F
8.297	0.000	tNET	RR	1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.552	0.869	tNET	RR	1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
11.517	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
11.453	-0.064	tSu		1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-2.173
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.650%; route: 2.359, 63.350%
Arrival Data Path Delay	cell: 1.585, 34.664%; route: 2.605, 56.971%; tC2Q: 0.382, 8.365%
Required Clock Path Delay	cell: 0.683, 43.979%; route: 0.869, 56.021%

Path6

Path Summary:

Slack	3.226
Data Arrival Time	8.009
Data Required Time	11.234
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.355	0.165	tNET	RR	1	R23C52[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
7.871	0.516	tINS	RR	1	R23C52[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
8.009	0.137	tNET	RR	1	R23C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.581	0.898	tNET	RR	1	R23C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
11.546	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
11.234	-0.311	tSu		1	R23C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-2.148
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.811, 42.319%; route: 2.086, 48.744%; tC2Q: 0.382, 8.937%
Required Clock Path Delay	cell: 0.683, 43.179%; route: 0.898, 56.821%

Path7

Path Summary:

Slack	3.266
Data Arrival Time	8.214
Data Required Time	11.479
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.687	0.497	tNET	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n331_s1/I3
8.214	0.526	tINS	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n331_s1/F
8.214	0.000	tNET	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
11.543	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
11.479	-0.064	tSu		1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-2.151
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.821, 40.608%; route: 2.281, 50.864%; tC2Q: 0.382, 8.528%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path8

Path Summary:

Slack	3.331
Data Arrival Time	8.149
Data Required Time	11.479
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.687	0.497	tNET	RR	1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n330_s1/I3
8.149	0.461	tINS	RR	1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n330_s1/F
8.149	0.000	tNET	RR	1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
11.543	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
11.479	-0.064	tSu		1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-2.151
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.756, 39.734%; route: 2.281, 51.612%; tC2Q: 0.382, 8.654%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path9

Path Summary:

Slack	3.359
Data Arrival Time	7.877
Data Required Time	11.237
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.734	2.369	tNET	RR	1	R20C46[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/CLK
4.116	0.382	tC2Q	RR	3	R20C46[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q
5.005	0.889	tNET	RR	1	R21C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I3
5.531	0.526	tINS	RR	1	R21C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
5.669	0.137	tNET	RR	1	R21C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
6.195	0.526	tINS	RR	3	R21C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
6.735	0.540	tNET	RR	1	R22C52[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
7.150	0.415	tINS	RR	1	R22C52[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
7.877	0.728	tNET	RR	1	R22C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.583	0.901	tNET	RR	1	R22C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
11.548	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
11.237	-0.311	tSu		1	R22C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-2.151
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.558%; route: 2.369, 63.442%
Arrival Data Path Delay	cell: 1.467, 35.415%; route: 2.294, 55.354%; tC2Q: 0.382, 9.231%
Required Clock Path Delay	cell: 0.683, 43.111%; route: 0.901, 56.889%

Path10

Path Summary:

Slack	3.411
Data Arrival Time	8.069
Data Required Time	11.479
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.552	0.363	tNET	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n336_s1/I2
8.069	0.516	tINS	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n336_s1/F
8.069	0.000	tNET	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
11.543	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
11.479	-0.064	tSu		1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-2.151
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.811, 41.734%; route: 2.146, 49.453%; tC2Q: 0.382, 8.813%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path11

Path Summary:

Slack	3.423
Data Arrival Time	8.071
Data Required Time	11.494
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.545	0.355	tNET	RR	1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n337_s1/I3
8.071	0.526	tINS	RR	1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n337_s1/F
8.071	0.000	tNET	RR	1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.592	0.910	tNET	RR	1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
11.557	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
11.494	-0.064	tSu		1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.821, 41.940%; route: 2.139, 49.252%; tC2Q: 0.382, 8.808%
Required Clock Path Delay	cell: 0.683, 42.857%; route: 0.910, 57.143%

Path12

Path Summary:

Slack	3.528
Data Arrival Time	7.972
Data Required Time	11.500
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.682	0.492	tNET	RR	1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n338_s1/I2
7.972	0.290	tINS	RF	1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n338_s1/F
7.972	0.000	tNET	FF	1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.592	0.910	tNET	RR	1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
11.557	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
11.500	-0.058	tSu		1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.585, 37.349%; route: 2.276, 53.638%; tC2Q: 0.382, 9.013%
Required Clock Path Delay	cell: 0.683, 42.857%; route: 0.910, 57.143%

Path13

Path Summary:

Slack	3.549
Data Arrival Time	7.945
Data Required Time	11.494
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.682	0.492	tNET	RR	1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n333_s1/I2
7.945	0.262	tINS	RR	1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n333_s1/F
7.945	0.000	tNET	RR	1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.592	0.910	tNET	RR	1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
11.557	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
11.494	-0.064	tSu		1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.558, 36.940%; route: 2.276, 53.988%; tC2Q: 0.382, 9.072%
Required Clock Path Delay	cell: 0.683, 42.857%; route: 0.910, 57.143%

Path14

Path Summary:

Slack	3.578
Data Arrival Time	7.866
Data Required Time	11.444
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.724	2.359	tNET	RR	1	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.107	0.382	tC2Q	RR	2	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.763	1.656	tNET	RR	2	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/I1
6.326	0.563	tINS	RF	1	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/COUT
6.326	0.000	tNET	FF	2	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/CIN
6.376	0.050	tINS	FR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/COUT
6.376	0.000	tNET	RR	2	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/CIN
6.426	0.050	tINS	RR	5	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/COUT
7.349	0.924	tNET	RR	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/n1884_s2/I3
7.866	0.516	tINS	RR	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/n1884_s2/F
7.866	0.000	tNET	RR	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.542	0.860	tNET	RR	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
11.507	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
11.444	-0.064	tSu		1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-2.182
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.650%; route: 2.359, 63.350%
Arrival Data Path Delay	cell: 1.179, 28.464%; route: 2.580, 62.300%; tC2Q: 0.382, 9.236%
Required Clock Path Delay	cell: 0.683, 44.246%; route: 0.860, 55.754%

Path15

Path Summary:

Slack	3.675
Data Arrival Time	7.819
Data Required Time	11.494
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.357	0.168	tNET	RR	1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n335_s1/I2
7.819	0.461	tINS	RR	1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n335_s1/F
7.819	0.000	tNET	RR	1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.592	0.910	tNET	RR	1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
11.557	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
11.494	-0.064	tSu		1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.756, 42.940%; route: 1.951, 47.708%; tC2Q: 0.382, 9.352%
Required Clock Path Delay	cell: 0.683, 42.857%; route: 0.910, 57.143%

Path16

Path Summary:

Slack	3.675
Data Arrival Time	7.819
Data Required Time	11.494
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.357	0.168	tNET	RR	1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n334_s3/I3
7.819	0.461	tINS	RR	1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n334_s3/F
7.819	0.000	tNET	RR	1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.592	0.910	tNET	RR	1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
11.557	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
11.494	-0.064	tSu		1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.756, 42.940%; route: 1.951, 47.708%; tC2Q: 0.382, 9.352%
Required Clock Path Delay	cell: 0.683, 42.857%; route: 0.910, 57.143%

Path17

Path Summary:

Slack	3.675
Data Arrival Time	7.819
Data Required Time	11.494
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/I0
7.190	0.516	tINS	RR	11	R22C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s5/F
7.357	0.168	tNET	RR	1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n332_s1/I3
7.819	0.461	tINS	RR	1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n332_s1/F
7.819	0.000	tNET	RR	1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.592	0.910	tNET	RR	1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
11.557	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
11.494	-0.064	tSu		1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-2.136
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.756, 42.940%; route: 1.951, 47.708%; tC2Q: 0.382, 9.352%
Required Clock Path Delay	cell: 0.683, 42.857%; route: 0.910, 57.143%

Path18

Path Summary:

Slack	3.698
Data Arrival Time	7.779
Data Required Time	11.477
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.734	2.369	tNET	RR	1	R20C46[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/CLK
4.116	0.382	tC2Q	RR	3	R20C46[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q
5.005	0.889	tNET	RR	1	R21C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I3
5.531	0.526	tINS	RR	1	R21C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
5.669	0.137	tNET	RR	1	R21C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
6.195	0.526	tINS	RR	3	R21C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
7.252	1.058	tNET	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n220_s3/I1
7.779	0.526	tINS	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n220_s3/F
7.779	0.000	tNET	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.576	0.893	tNET	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
11.541	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
11.477	-0.064	tSu		1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-2.158
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.558%; route: 2.369, 63.442%
Arrival Data Path Delay	cell: 1.579, 39.030%; route: 2.084, 51.514%; tC2Q: 0.382, 9.456%
Required Clock Path Delay	cell: 0.683, 43.316%; route: 0.893, 56.684%

Path19

Path Summary:

Slack	4.114
Data Arrival Time	7.348
Data Required Time	11.462
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.724	2.359	tNET	RR	1	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.107	0.382	tC2Q	RR	2	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.763	1.656	tNET	RR	2	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/I1
6.326	0.563	tINS	RF	1	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/COUT
6.326	0.000	tNET	FF	2	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/CIN
6.376	0.050	tINS	FR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/COUT
6.376	0.000	tNET	RR	2	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/CIN
6.426	0.050	tINS	RR	5	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/COUT
6.832	0.406	tNET	RR	1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/n1885_s5/I2
7.348	0.516	tINS	RR	1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/n1885_s5/F
7.348	0.000	tNET	RR	1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.561	0.879	tNET	RR	1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
11.526	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
11.462	-0.064	tSu		1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-2.163
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.650%; route: 2.359, 63.350%
Arrival Data Path Delay	cell: 1.179, 32.528%; route: 2.063, 56.916%; tC2Q: 0.382, 10.555%
Required Clock Path Delay	cell: 0.683, 43.715%; route: 0.879, 56.285%

Path20

Path Summary:

Slack	4.180
Data Arrival Time	7.284
Data Required Time	11.464
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.724	2.359	tNET	RR	1	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.107	0.382	tC2Q	RR	2	R20C45[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.763	1.656	tNET	RR	2	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/I1
6.326	0.563	tINS	RF	1	R16C53[0][B]	gw_gao_inst_0/u_la0_top/n1861_s0/COUT
6.326	0.000	tNET	FF	2	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/CIN
6.376	0.050	tINS	FR	1	R16C53[1][A]	gw_gao_inst_0/u_la0_top/n1862_s0/COUT
6.376	0.000	tNET	RR	2	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/CIN
6.426	0.050	tINS	RR	5	R16C53[1][B]	gw_gao_inst_0/u_la0_top/n1863_s0/COUT
7.022	0.596	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/n1904_s2/I1
7.284	0.262	tINS	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/n1904_s2/F
7.284	0.000	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.563	0.881	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
11.528	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_s0
11.464	-0.064	tSu		1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-2.161
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.650%; route: 2.359, 63.350%
Arrival Data Path Delay	cell: 0.925, 25.983%; route: 2.253, 63.272%; tC2Q: 0.382, 10.744%
Required Clock Path Delay	cell: 0.683, 43.663%; route: 0.881, 56.337%

Path21

Path Summary:

Slack	4.349
Data Arrival Time	7.135
Data Required Time	11.484
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.729	2.364	tNET	RR	1	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
4.111	0.382	tC2Q	RR	2	R22C46[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
5.047	0.936	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/I3
5.310	0.262	tINS	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s10/F
5.637	0.327	tNET	RR	1	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/I1
6.154	0.516	tINS	RR	2	R22C48[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s7/F
6.674	0.520	tNET	RR	1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n339_s2/I1
7.135	0.461	tINS	RR	1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n339_s2/F
7.135	0.000	tNET	RR	1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.583	0.901	tNET	RR	1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
11.548	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
11.484	-0.064	tSu		1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-2.146
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 36.607%; route: 2.364, 63.393%
Arrival Data Path Delay	cell: 1.240, 36.404%; route: 1.784, 52.367%; tC2Q: 0.382, 11.229%
Required Clock Path Delay	cell: 0.683, 43.111%; route: 0.901, 56.889%

Path22

Path Summary:

Slack	4.726
Data Arrival Time	6.729
Data Required Time	11.455
From	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.696	2.331	tNET	RR	1	R16C46[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0/CLK
4.078	0.382	tC2Q	RR	6	R16C46[1][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_2_s0/Q
5.142	1.064	tNET	RR	2	R16C52[1][A]	gw_gao_inst_0/u_la0_top/n1834_s10/I0
5.698	0.556	tINS	RF	1	R16C52[1][A]	gw_gao_inst_0/u_la0_top/n1834_s10/COUT
6.268	0.570	tNET	FF	1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg1_s0/I3
6.729	0.461	tINS	FR	1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg1_s0/F
6.729	0.000	tNET	RR	1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.554	0.871	tNET	RR	1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
11.519	-0.035	tUnc				gw_gao_inst_0/u_la0_top/start_reg_s0
11.455	-0.064	tSu		1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-2.142
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 36.936%; route: 2.331, 63.064%
Arrival Data Path Delay	cell: 1.017, 33.539%; route: 1.634, 53.852%; tC2Q: 0.382, 12.608%
Required Clock Path Delay	cell: 0.683, 43.926%; route: 0.871, 56.074%

Path23

Path Summary:

Slack	4.731
Data Arrival Time	6.796
Data Required Time	11.527
From	uart_data_tx/cnt_6_s1
To	uart_data_tx/Tx_Done_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.683	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.548	0.866	tNET	RR	1	R15C42[1][B]	uart_data_tx/cnt_6_s1/CLK
1.931	0.382	tC2Q	RR	3	R15C42[1][B]	uart_data_tx/cnt_6_s1/Q
2.418	0.487	tNET	RR	1	R15C43[1][A]	uart_data_tx/n51_s2/I1
2.879	0.461	tINS	RR	3	R15C43[1][A]	uart_data_tx/n51_s2/F
3.039	0.160	tNET	RR	1	R14C43[3][B]	uart_data_tx/n80_s5/I0
3.537	0.498	tINS	RR	1	R14C43[3][B]	uart_data_tx/n80_s5/F
6.796	3.259	tNET	RR	1	IOT89[B]	uart_data_tx/Tx_Done_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.591	0.908	tNET	RR	1	IOT89[B]	uart_data_tx/Tx_Done_s0/CLK
11.527	-0.064	tSu		1	IOT89[B]	uart_data_tx/Tx_Done_s0

Path Statistics:

Clock Skew	0.043
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 44.086%; route: 0.866, 55.914%
Arrival Data Path Delay	cell: 0.959, 18.271%; route: 3.906, 74.440%; tC2Q: 0.382, 7.289%
Required Clock Path Delay	cell: 0.683, 42.908%; route: 0.908, 57.092%

Path24

Path Summary:

Slack	4.869
Data Arrival Time	6.411
Data Required Time	11.279
From	uart_data_tx/state_1_s0
To	uart_data_tx/Tx_Done_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.683	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.559	0.877	tNET	RR	1	R16C41[0][B]	uart_data_tx/state_1_s0/CLK
1.927	0.368	tC2Q	RF	23	R16C41[0][B]	uart_data_tx/state_1_s0/Q
2.764	0.837	tNET	FF	1	R13C43[1][A]	uart_data_tx/Tx_Done_s3/I1
3.291	0.526	tINS	FR	1	R13C43[1][A]	uart_data_tx/Tx_Done_s3/F
6.411	3.120	tNET	RR	1	IOT89[B]	uart_data_tx/Tx_Done_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.591	0.908	tNET	RR	1	IOT89[B]	uart_data_tx/Tx_Done_s0/CLK
11.279	-0.311	tSu		1	IOT89[B]	uart_data_tx/Tx_Done_s0

Path Statistics:

Clock Skew	0.031
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 43.768%; route: 0.877, 56.232%
Arrival Data Path Delay	cell: 0.526, 10.848%; route: 3.958, 81.577%; tC2Q: 0.368, 7.575%
Required Clock Path Delay	cell: 0.683, 42.908%; route: 0.908, 57.092%

Path25

Path Summary:

Slack	4.873
Data Arrival Time	6.616
Data Required Time	11.489
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
3.722	2.357	tNET	RR	1	R21C47[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK
4.104	0.382	tC2Q	RR	3	R21C47[3][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q
6.154	2.050	tNET	RR	1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s3/I1
6.616	0.461	tINS	RR	1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s3/F
6.616	0.000	tNET	RR	1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.587	0.905	tNET	RR	1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
11.552	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
11.489	-0.064	tSu		1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	-2.134
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.365, 36.675%; route: 2.357, 63.325%
Arrival Data Path Delay	cell: 0.461, 15.940%; route: 2.050, 70.842%; tC2Q: 0.382, 13.218%
Required Clock Path Delay	cell: 0.683, 42.992%; route: 0.905, 57.008%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.020
Data Arrival Time	51.611
Data Required Time	52.632
From	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	Clk:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					Clk
50.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
50.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
51.050	0.375	tNET	RR	1	R18C52[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
51.230	0.180	tC2Q	RR	3	R18C52[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q
51.354	0.124	tNET	RR	1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/n1896_s1/I0
51.611	0.257	tINS	RF	1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/n1896_s1/F
51.611	0.000	tNET	FF	1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.595	1.244	tNET	RR	1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
52.630	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
52.632	0.001	tHld		1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	1.545
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%
Arrival Data Path Delay	cell: 0.257, 45.880%; route: 0.124, 22.049%; tC2Q: 0.180, 32.071%
Required Clock Path Delay	cell: 1.351, 52.054%; route: 1.244, 47.946%

Path2

Path Summary:

Slack	0.068
Data Arrival Time	1.370
Data Required Time	1.302
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.064	0.388	tNET	RR	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK
1.244	0.180	tC2Q	RR	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q
1.370	0.126	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.053	0.378	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.302	0.249	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.491%; route: 0.388, 36.509%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.675, 64.150%; route: 0.378, 35.850%

Path3

Path Summary:

Slack	0.083
Data Arrival Time	1.380
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.074	0.398	tNET	RR	1	R24C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
1.254	0.180	tC2Q	RR	1	R24C45[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
1.380	0.126	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 62.899%; route: 0.398, 37.101%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path4

Path Summary:

Slack	0.088
Data Arrival Time	1.380
Data Required Time	1.292
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.074	0.398	tNET	RR	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
1.254	0.180	tC2Q	RR	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
1.380	0.126	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.043	0.368	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.292	0.249	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.031
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 62.899%; route: 0.398, 37.101%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay	cell: 0.675, 64.765%; route: 0.368, 35.235%

Path5

Path Summary:

Slack	0.133
Data Arrival Time	1.425
Data Required Time	1.292
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.066	0.391	tNET	RR	1	R23C51[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK
1.246	0.180	tC2Q	RR	1	R23C51[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q
1.425	0.179	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.043	0.368	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.292	0.249	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.360%; route: 0.391, 36.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 49.826%; tC2Q: 0.180, 50.174%
Required Clock Path Delay	cell: 0.675, 64.765%; route: 0.368, 35.235%

Path6

Path Summary:

Slack	0.133
Data Arrival Time	1.425
Data Required Time	1.292
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.066	0.391	tNET	RR	1	R23C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
1.246	0.180	tC2Q	RR	1	R23C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
1.425	0.179	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.043	0.368	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.292	0.249	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.360%; route: 0.391, 36.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 49.826%; tC2Q: 0.180, 50.174%
Required Clock Path Delay	cell: 0.675, 64.765%; route: 0.368, 35.235%

Path7

Path Summary:

Slack	0.186
Data Arrival Time	1.483
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.067	0.391	tNET	RR	1	R25C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/CLK
1.247	0.180	tC2Q	RR	1	R25C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q
1.483	0.236	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.323%; route: 0.391, 36.677%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path8

Path Summary:

Slack	0.196
Data Arrival Time	1.493
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q
1.493	0.244	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path9

Path Summary:

Slack	0.196
Data Arrival Time	1.493
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
1.493	0.244	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path10

Path Summary:

Slack	0.196
Data Arrival Time	1.493
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q
1.493	0.244	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path11

Path Summary:

Slack	0.196
Data Arrival Time	1.493
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q
1.493	0.244	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path12

Path Summary:

Slack	0.196
Data Arrival Time	1.493
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C44[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C44[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q
1.493	0.244	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path13

Path Summary:

Slack	0.203
Data Arrival Time	1.495
Data Required Time	1.292
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.076	0.401	tNET	RR	1	R23C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/CLK
1.256	0.180	tC2Q	RR	1	R23C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q
1.495	0.239	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.043	0.368	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.292	0.249	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.033
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 62.772%; route: 0.401, 37.228%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 57.015%; tC2Q: 0.180, 42.985%
Required Clock Path Delay	cell: 0.675, 64.765%; route: 0.368, 35.235%

Path14

Path Summary:

Slack	0.218
Data Arrival Time	1.389
Data Required Time	1.171
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.249	0.180	tC2Q	RR	7	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.389	0.140	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.053	0.378	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.171	0.118	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 43.750%; tC2Q: 0.180, 56.250%
Required Clock Path Delay	cell: 0.675, 64.150%; route: 0.378, 35.850%

Path15

Path Summary:

Slack	0.218
Data Arrival Time	1.389
Data Required Time	1.171
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.249	0.180	tC2Q	RR	7	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.389	0.140	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/ADA[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.053	0.378	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.171	0.118	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.016
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 43.750%; tC2Q: 0.180, 56.250%
Required Clock Path Delay	cell: 0.675, 64.150%; route: 0.378, 35.850%

Path16

Path Summary:

Slack	0.225
Data Arrival Time	1.391
Data Required Time	1.166
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.249	0.180	tC2Q	RR	7	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.391	0.142	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.166	0.118	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 44.186%; tC2Q: 0.180, 55.814%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path17

Path Summary:

Slack	0.225
Data Arrival Time	1.391
Data Required Time	1.166
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.249	0.180	tC2Q	RR	7	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.391	0.142	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.166	0.118	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.142, 44.186%; tC2Q: 0.180, 55.814%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path18

Path Summary:

Slack	0.289
Data Arrival Time	1.586
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q
1.586	0.337	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.337, 65.217%; tC2Q: 0.180, 34.783%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path19

Path Summary:

Slack	0.289
Data Arrival Time	1.586
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q
1.586	0.337	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.337, 65.217%; tC2Q: 0.180, 34.783%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path20

Path Summary:

Slack	0.289
Data Arrival Time	1.586
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.069	0.393	tNET	RR	1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
1.249	0.180	tC2Q	RR	1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
1.586	0.337	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.194%; route: 0.393, 36.806%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.337, 65.217%; tC2Q: 0.180, 34.783%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path21

Path Summary:

Slack	0.293
Data Arrival Time	1.595
Data Required Time	1.302
From	gw_gao_inst_0/u_la0_top/triger_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.055	0.380	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.235	0.180	tC2Q	RR	11	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/Q
1.595	0.360	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.053	0.378	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.302	0.249	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 64.017%; route: 0.380, 35.983%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.360, 66.667%; tC2Q: 0.180, 33.333%
Required Clock Path Delay	cell: 0.675, 64.150%; route: 0.378, 35.850%

Path22

Path Summary:

Slack	0.308
Data Arrival Time	1.610
Data Required Time	1.302
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.071	0.396	tNET	RR	1	R23C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK
1.251	0.180	tC2Q	RR	1	R23C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q
1.610	0.359	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.053	0.378	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.302	0.249	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.065%; route: 0.396, 36.935%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.359, 66.589%; tC2Q: 0.180, 33.411%
Required Clock Path Delay	cell: 0.675, 64.150%; route: 0.378, 35.850%

Path23

Path Summary:

Slack	0.308
Data Arrival Time	1.610
Data Required Time	1.302
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.071	0.396	tNET	RR	1	R23C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK
1.251	0.180	tC2Q	RR	1	R23C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q
1.610	0.359	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.053	0.378	tNET	RR	1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.302	0.249	tHld		1	BSRAM_R28[16]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.065%; route: 0.396, 36.935%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.359, 66.589%; tC2Q: 0.180, 33.411%
Required Clock Path Delay	cell: 0.675, 64.150%; route: 0.378, 35.850%

Path24

Path Summary:

Slack	0.310
Data Arrival Time	1.607
Data Required Time	1.297
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.071	0.396	tNET	RR	1	R23C44[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/CLK
1.251	0.180	tC2Q	RR	1	R23C44[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q
1.607	0.356	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.048	0.373	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.297	0.249	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.065%; route: 0.396, 36.935%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566%
Required Clock Path Delay	cell: 0.675, 64.456%; route: 0.373, 35.544%

Path25

Path Summary:

Slack	0.313
Data Arrival Time	1.605
Data Required Time	1.292
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.066	0.391	tNET	RR	1	R23C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
1.246	0.180	tC2Q	RR	1	R23C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.605	0.359	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.043	0.368	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.292	0.249	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 63.360%; route: 0.391, 36.640%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.359, 66.589%; tC2Q: 0.180, 33.411%
Required Clock Path Delay	cell: 0.675, 64.765%; route: 0.368, 35.235%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.434
Data Arrival Time	7.780
Data Required Time	11.214
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.780	0.781	tNET	FF	1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.561	0.879	tNET	RR	1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
11.214	-0.347	tSu		1	R17C53[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.781, 63.841%; tC2Q: 0.442, 36.159%
Required Clock Path Delay	cell: 0.683, 43.715%; route: 0.879, 56.285%

Path2

Path Summary:

Slack	3.479
Data Arrival Time	7.752
Data Required Time	11.231
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.752	0.753	tNET	FF	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
11.231	-0.347	tSu		1	R24C52[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.753, 62.990%; tC2Q: 0.442, 37.010%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path3

Path Summary:

Slack	3.479
Data Arrival Time	7.752
Data Required Time	11.231
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.752	0.753	tNET	FF	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
11.231	-0.347	tSu		1	R24C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.753, 62.990%; tC2Q: 0.442, 37.010%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path4

Path Summary:

Slack	3.479
Data Arrival Time	7.752
Data Required Time	11.231
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.752	0.753	tNET	FF	1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
11.231	-0.347	tSu		1	R24C52[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.753, 62.990%; tC2Q: 0.442, 37.010%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path5

Path Summary:

Slack	3.479
Data Arrival Time	7.752
Data Required Time	11.231
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.752	0.753	tNET	FF	1	R24C52[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.578	0.896	tNET	RR	1	R24C52[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
11.231	-0.347	tSu		1	R24C52[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.753, 62.990%; tC2Q: 0.442, 37.010%
Required Clock Path Delay	cell: 0.683, 43.248%; route: 0.896, 56.752%

Path6

Path Summary:

Slack	3.481
Data Arrival Time	7.752
Data Required Time	11.233
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.752	0.753	tNET	FF	1	R23C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.581	0.898	tNET	RR	1	R23C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
11.233	-0.347	tSu		1	R23C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.024
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.753, 62.990%; tC2Q: 0.442, 37.010%
Required Clock Path Delay	cell: 0.683, 43.179%; route: 0.898, 56.821%

Path7

Path Summary:

Slack	3.486
Data Arrival Time	7.754
Data Required Time	11.240
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.754	0.755	tNET	FF	1	R24C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.587	0.905	tNET	RR	1	R24C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
11.240	-0.347	tSu		1	R24C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.031
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.755, 63.058%; tC2Q: 0.442, 36.942%
Required Clock Path Delay	cell: 0.683, 42.992%; route: 0.905, 57.008%

Path8

Path Summary:

Slack	3.486
Data Arrival Time	7.754
Data Required Time	11.240
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.754	0.755	tNET	FF	1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.587	0.905	tNET	RR	1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
11.240	-0.347	tSu		1	R24C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	0.031
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.755, 63.058%; tC2Q: 0.442, 36.942%
Required Clock Path Delay	cell: 0.683, 42.992%; route: 0.905, 57.008%

Path9

Path Summary:

Slack	3.488
Data Arrival Time	7.754
Data Required Time	11.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.754	0.755	tNET	FF	1	R23C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.590	0.907	tNET	RR	1	R23C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
11.243	-0.347	tSu		1	R23C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.034
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.755, 63.058%; tC2Q: 0.442, 36.942%
Required Clock Path Delay	cell: 0.683, 42.925%; route: 0.907, 57.075%

Path10

Path Summary:

Slack	3.488
Data Arrival Time	7.754
Data Required Time	11.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.754	0.755	tNET	FF	1	R23C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.590	0.907	tNET	RR	1	R23C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
11.243	-0.347	tSu		1	R23C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.034
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.755, 63.058%; tC2Q: 0.442, 36.942%
Required Clock Path Delay	cell: 0.683, 42.925%; route: 0.907, 57.075%

Path11

Path Summary:

Slack	3.488
Data Arrival Time	7.754
Data Required Time	11.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.754	0.755	tNET	FF	1	R23C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.590	0.907	tNET	RR	1	R23C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
11.243	-0.347	tSu		1	R23C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.034
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.755, 63.058%; tC2Q: 0.442, 36.942%
Required Clock Path Delay	cell: 0.683, 42.925%; route: 0.907, 57.075%

Path12

Path Summary:

Slack	3.488
Data Arrival Time	7.754
Data Required Time	11.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.754	0.755	tNET	FF	1	R23C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.590	0.907	tNET	RR	1	R23C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
11.243	-0.347	tSu		1	R23C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.034
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.755, 63.058%; tC2Q: 0.442, 36.942%
Required Clock Path Delay	cell: 0.683, 42.925%; route: 0.907, 57.075%

Path13

Path Summary:

Slack	3.592
Data Arrival Time	7.624
Data Required Time	11.216
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.624	0.625	tNET	FF	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.563	0.881	tNET	RR	1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
11.216	-0.347	tSu		1	R18C53[0][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.625, 58.548%; tC2Q: 0.442, 41.452%
Required Clock Path Delay	cell: 0.683, 43.663%; route: 0.881, 56.337%

Path14

Path Summary:

Slack	3.599
Data Arrival Time	7.596
Data Required Time	11.195
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.596	0.597	tNET	FF	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.542	0.860	tNET	RR	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
11.195	-0.347	tSu		1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.597, 57.452%; tC2Q: 0.442, 42.548%
Required Clock Path Delay	cell: 0.683, 44.246%; route: 0.860, 55.754%

Path15

Path Summary:

Slack	3.609
Data Arrival Time	7.631
Data Required Time	11.241
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.631	0.632	tNET	FF	1	R20C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.588	0.906	tNET	RR	1	R20C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
11.241	-0.347	tSu		1	R20C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.632, 58.837%; tC2Q: 0.442, 41.163%
Required Clock Path Delay	cell: 0.683, 42.975%; route: 0.906, 57.025%

Path16

Path Summary:

Slack	3.619
Data Arrival Time	7.631
Data Required Time	11.250
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.631	0.632	tNET	FF	1	R20C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.597	0.915	tNET	RR	1	R20C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
11.250	-0.347	tSu		1	R20C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.041
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.632, 58.837%; tC2Q: 0.442, 41.163%
Required Clock Path Delay	cell: 0.683, 42.723%; route: 0.915, 57.277%

Path17

Path Summary:

Slack	3.619
Data Arrival Time	7.631
Data Required Time	11.250
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.631	0.632	tNET	FF	1	R20C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.597	0.915	tNET	RR	1	R20C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
11.250	-0.347	tSu		1	R20C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.041
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.632, 58.837%; tC2Q: 0.442, 41.163%
Required Clock Path Delay	cell: 0.683, 42.723%; route: 0.915, 57.277%

Path18

Path Summary:

Slack	3.690
Data Arrival Time	7.529
Data Required Time	11.219
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.529	0.530	tNET	FF	1	R25C51[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.566	0.884	tNET	RR	1	R25C51[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
11.219	-0.347	tSu		1	R25C51[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.530, 54.513%; tC2Q: 0.442, 45.487%
Required Clock Path Delay	cell: 0.683, 43.575%; route: 0.884, 56.425%

Path19

Path Summary:

Slack	3.690
Data Arrival Time	7.529
Data Required Time	11.219
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.529	0.530	tNET	FF	1	R25C51[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.566	0.884	tNET	RR	1	R25C51[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
11.219	-0.347	tSu		1	R25C51[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.530, 54.513%; tC2Q: 0.442, 45.487%
Required Clock Path Delay	cell: 0.683, 43.575%; route: 0.884, 56.425%

Path20

Path Summary:

Slack	3.690
Data Arrival Time	7.529
Data Required Time	11.219
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.529	0.530	tNET	FF	1	R25C51[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.566	0.884	tNET	RR	1	R25C51[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
11.219	-0.347	tSu		1	R25C51[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	0.010
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.530, 54.513%; tC2Q: 0.442, 45.487%
Required Clock Path Delay	cell: 0.683, 43.575%; route: 0.884, 56.425%

Path21

Path Summary:

Slack	3.694
Data Arrival Time	7.542
Data Required Time	11.236
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.542	0.543	tNET	FF	1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.583	0.901	tNET	RR	1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
11.236	-0.347	tSu		1	R22C52[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.027
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.543, 55.105%; tC2Q: 0.442, 44.895%
Required Clock Path Delay	cell: 0.683, 43.111%; route: 0.901, 56.889%

Path22

Path Summary:

Slack	3.694
Data Arrival Time	7.542
Data Required Time	11.236
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.542	0.543	tNET	FF	1	R22C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.583	0.901	tNET	RR	1	R22C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
11.236	-0.347	tSu		1	R22C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.027
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.543, 55.105%; tC2Q: 0.442, 44.895%
Required Clock Path Delay	cell: 0.683, 43.111%; route: 0.901, 56.889%

Path23

Path Summary:

Slack	3.694
Data Arrival Time	7.542
Data Required Time	11.236
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.542	0.543	tNET	FF	1	R22C52[3][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.583	0.901	tNET	RR	1	R22C52[3][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
11.236	-0.347	tSu		1	R22C52[3][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.027
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.543, 55.105%; tC2Q: 0.442, 44.895%
Required Clock Path Delay	cell: 0.683, 43.111%; route: 0.901, 56.889%

Path24

Path Summary:

Slack	3.699
Data Arrival Time	7.529
Data Required Time	11.228
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.529	0.530	tNET	FF	1	R25C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.576	0.893	tNET	RR	1	R25C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
11.228	-0.347	tSu		1	R25C52[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.530, 54.513%; tC2Q: 0.442, 45.487%
Required Clock Path Delay	cell: 0.683, 43.316%; route: 0.893, 56.684%

Path25

Path Summary:

Slack	3.699
Data Arrival Time	7.529
Data Required Time	11.228
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.688	0.688	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.556	0.869	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.999	0.442	tC2Q	FF	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.529	0.530	tNET	FF	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.682	0.683	tINS	RR	335	IOB29[A]	Clk_ibuf/O
11.576	0.893	tNET	RR	1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
11.228	-0.347	tSu		1	R25C52[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 44.177%; route: 0.869, 55.823%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.530, 54.513%; tC2Q: 0.442, 45.487%
Required Clock Path Delay	cell: 0.683, 43.316%; route: 0.893, 56.684%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.201
Data Arrival Time	56.643
Data Required Time	52.442
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	Clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
55.000	55.000					active clock edge time
55.000	0.000					Clk
55.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
55.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
56.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
56.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
56.643	0.389	tNET	RR	1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.595	1.244	tNET	RR	1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
52.630	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
52.442	-0.189	tHld		1	R17C52[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	1.538
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.389, 66.311%; tC2Q: 0.198, 33.689%
Required Clock Path Delay	cell: 1.351, 52.054%; route: 1.244, 47.946%

Path2

Path Summary:

Slack	4.208
Data Arrival Time	56.648
Data Required Time	52.440
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0
Launch Clk	Clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
55.000	55.000					active clock edge time
55.000	0.000					Clk
55.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
55.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
56.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
56.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
56.648	0.394	tNET	RR	1	R16C52[2][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.594	1.243	tNET	RR	1	R16C52[2][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK
52.629	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0
52.440	-0.189	tHld		1	R16C52[2][B]	gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0

Path Statistics:

Clock Skew	1.537
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.394, 66.596%; tC2Q: 0.198, 33.404%
Required Clock Path Delay	cell: 1.351, 52.085%; route: 1.243, 47.915%

Path3

Path Summary:

Slack	4.328
Data Arrival Time	56.763
Data Required Time	52.435
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0
Launch Clk	Clk:[F]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
55.000	55.000					active clock edge time
55.000	0.000					Clk
55.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
55.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
56.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
56.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
56.763	0.509	tNET	RR	1	R16C51[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351	0.675	tINS	RR	244	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.589	1.238	tNET	RR	1	R16C51[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK
52.624	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0
52.435	-0.189	tHld		1	R16C51[1][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0

Path Statistics:

Clock Skew	1.532
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.509, 72.035%; tC2Q: 0.198, 27.965%
Required Clock Path Delay	cell: 1.351, 52.186%; route: 1.238, 47.814%

Path4

Path Summary:

Slack	5.646
Data Arrival Time	6.511
Data Required Time	0.865
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.511	0.256	tNET	RR	1	R17C49[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.054	0.378	tNET	RR	1	R17C49[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.865	-0.189	tHld		1	R17C49[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.256, 56.474%; tC2Q: 0.198, 43.526%
Required Clock Path Delay	cell: 0.675, 64.112%; route: 0.378, 35.888%

Path5

Path Summary:

Slack	5.646
Data Arrival Time	6.511
Data Required Time	0.865
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.511	0.256	tNET	RR	1	R17C49[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.054	0.378	tNET	RR	1	R17C49[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.865	-0.189	tHld		1	R17C49[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.256, 56.474%; tC2Q: 0.198, 43.526%
Required Clock Path Delay	cell: 0.675, 64.112%; route: 0.378, 35.888%

Path6

Path Summary:

Slack	5.656
Data Arrival Time	6.516
Data Required Time	0.860
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.516	0.261	tNET	RR	1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.049	0.373	tNET	RR	1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.860	-0.189	tHld		1	R17C50[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.008
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.948%; tC2Q: 0.198, 43.052%
Required Clock Path Delay	cell: 0.675, 64.418%; route: 0.373, 35.582%

Path7

Path Summary:

Slack	5.656
Data Arrival Time	6.516
Data Required Time	0.860
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.516	0.261	tNET	RR	1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.049	0.373	tNET	RR	1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
0.860	-0.189	tHld		1	R17C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.008
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.948%; tC2Q: 0.198, 43.052%
Required Clock Path Delay	cell: 0.675, 64.418%; route: 0.373, 35.582%

Path8

Path Summary:

Slack	5.667
Data Arrival Time	6.528
Data Required Time	0.861
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.050	0.375	tNET	RR	1	R18C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.861	-0.189	tHld		1	R18C52[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path9

Path Summary:

Slack	5.667
Data Arrival Time	6.528
Data Required Time	0.861
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C52[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.050	0.375	tNET	RR	1	R18C52[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.861	-0.189	tHld		1	R18C52[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path10

Path Summary:

Slack	5.667
Data Arrival Time	6.528
Data Required Time	0.861
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C52[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.050	0.375	tNET	RR	1	R18C52[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.861	-0.189	tHld		1	R18C52[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path11

Path Summary:

Slack	5.667
Data Arrival Time	6.528
Data Required Time	0.861
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.050	0.375	tNET	RR	1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.861	-0.189	tHld		1	R18C52[1][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.007
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.322%; route: 0.375, 35.678%

Path12

Path Summary:

Slack	5.672
Data Arrival Time	6.528
Data Required Time	0.856
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C51[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.045	0.370	tNET	RR	1	R18C51[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.856	-0.189	tHld		1	R18C51[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%

Path13

Path Summary:

Slack	5.672
Data Arrival Time	6.528
Data Required Time	0.856
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C51[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.045	0.370	tNET	RR	1	R18C51[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.856	-0.189	tHld		1	R18C51[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%

Path14

Path Summary:

Slack	5.672
Data Arrival Time	6.528
Data Required Time	0.856
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C51[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.045	0.370	tNET	RR	1	R18C51[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.856	-0.189	tHld		1	R18C51[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%

Path15

Path Summary:

Slack	5.672
Data Arrival Time	6.528
Data Required Time	0.856
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C51[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.045	0.370	tNET	RR	1	R18C51[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.856	-0.189	tHld		1	R18C51[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%

Path16

Path Summary:

Slack	5.672
Data Arrival Time	6.528
Data Required Time	0.856
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C51[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.045	0.370	tNET	RR	1	R18C51[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.856	-0.189	tHld		1	R18C51[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%

Path17

Path Summary:

Slack	5.672
Data Arrival Time	6.528
Data Required Time	0.856
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.528	0.274	tNET	RR	1	R18C51[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.045	0.370	tNET	RR	1	R18C51[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.856	-0.189	tHld		1	R18C51[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 58.090%; tC2Q: 0.198, 41.910%
Required Clock Path Delay	cell: 0.675, 64.630%; route: 0.370, 35.370%

Path18

Path Summary:

Slack	5.719
Data Arrival Time	6.602
Data Required Time	0.883
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.602	0.347	tNET	RR	1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.072	0.396	tNET	RR	1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
0.883	-0.189	tHld		1	R25C53[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.015
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.347, 63.761%; tC2Q: 0.198, 36.239%
Required Clock Path Delay	cell: 0.675, 63.028%; route: 0.396, 36.972%

Path19

Path Summary:

Slack	5.719
Data Arrival Time	6.602
Data Required Time	0.883
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.602	0.347	tNET	RR	1	R25C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.072	0.396	tNET	RR	1	R25C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.883	-0.189	tHld		1	R25C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.015
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.347, 63.761%; tC2Q: 0.198, 36.239%
Required Clock Path Delay	cell: 0.675, 63.028%; route: 0.396, 36.972%

Path20

Path Summary:

Slack	5.723
Data Arrival Time	6.613
Data Required Time	0.890
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.613	0.358	tNET	RR	1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.078	0.403	tNET	RR	1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.890	-0.189	tHld		1	R22C53[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 64.454%; tC2Q: 0.198, 35.546%
Required Clock Path Delay	cell: 0.675, 62.644%; route: 0.403, 37.356%

Path21

Path Summary:

Slack	5.723
Data Arrival Time	6.613
Data Required Time	0.890
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.613	0.358	tNET	RR	1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.078	0.403	tNET	RR	1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.890	-0.189	tHld		1	R22C53[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 64.454%; tC2Q: 0.198, 35.546%
Required Clock Path Delay	cell: 0.675, 62.644%; route: 0.403, 37.356%

Path22

Path Summary:

Slack	5.723
Data Arrival Time	6.613
Data Required Time	0.890
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.613	0.358	tNET	RR	1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.078	0.403	tNET	RR	1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.890	-0.189	tHld		1	R22C53[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 64.454%; tC2Q: 0.198, 35.546%
Required Clock Path Delay	cell: 0.675, 62.644%; route: 0.403, 37.356%

Path23

Path Summary:

Slack	5.723
Data Arrival Time	6.613
Data Required Time	0.890
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.613	0.358	tNET	RR	1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.078	0.403	tNET	RR	1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.890	-0.189	tHld		1	R22C53[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 64.454%; tC2Q: 0.198, 35.546%
Required Clock Path Delay	cell: 0.675, 62.644%; route: 0.403, 37.356%

Path24

Path Summary:

Slack	5.723
Data Arrival Time	6.613
Data Required Time	0.890
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.613	0.358	tNET	RR	1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.078	0.403	tNET	RR	1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.890	-0.189	tHld		1	R22C53[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 64.454%; tC2Q: 0.198, 35.546%
Required Clock Path Delay	cell: 0.675, 62.644%; route: 0.403, 37.356%

Path25

Path Summary:

Slack	5.723
Data Arrival Time	6.613
Data Required Time	0.890
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	Clk:[F]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Clk
5.000	0.000	tCL	FF	1	IOB29[A]	Clk_ibuf/I
5.677	0.678	tINS	FF	335	IOB29[A]	Clk_ibuf/O
6.057	0.379	tNET	FF	1	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.254	0.198	tC2Q	FR	51	R18C50[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.613	0.358	tNET	RR	1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.675	0.675	tINS	RR	335	IOB29[A]	Clk_ibuf/O
1.078	0.403	tNET	RR	1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.890	-0.189	tHld		1	R22C53[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 64.104%; route: 0.379, 35.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 64.454%; tC2Q: 0.198, 35.546%
Required Clock Path Delay	cell: 0.675, 62.644%; route: 0.403, 37.356%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.486
Actual Width:	4.486
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.688	0.688	tINS	FF	Clk_ibuf/O
6.567	0.880	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.675	0.675	tINS	RR	Clk_ibuf/O
11.053	0.378	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW2

MPW Summary:

Slack:	3.490
Actual Width:	4.490
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.688	0.688	tINS	FF	Clk_ibuf/O
6.558	0.870	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.675	0.675	tINS	RR	Clk_ibuf/O
11.048	0.373	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	3.490
Actual Width:	4.490
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.688	0.688	tINS	FF	Clk_ibuf/O
6.558	0.870	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.675	0.675	tINS	RR	Clk_ibuf/O
11.048	0.373	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW4

MPW Summary:

Slack:	3.495
Actual Width:	4.495
Required Width:	1.000
Type:	Low Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.688	0.688	tINS	FF	Clk_ibuf/O
6.548	0.861	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.675	0.675	tINS	RR	Clk_ibuf/O
11.043	0.368	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW5

MPW Summary:

Slack:	3.497
Actual Width:	4.497
Required Width:	1.000
Type:	High Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
0.683	0.683	tINS	RR	Clk_ibuf/O
1.563	0.881	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.677	0.678	tINS	FF	Clk_ibuf/O
6.061	0.383	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW6

MPW Summary:

Slack:	3.502
Actual Width:	4.502
Required Width:	1.000
Type:	High Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
0.683	0.683	tINS	RR	Clk_ibuf/O
1.554	0.872	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.677	0.678	tINS	FF	Clk_ibuf/O
6.056	0.378	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW7

MPW Summary:

Slack:	3.502
Actual Width:	4.502
Required Width:	1.000
Type:	High Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
0.683	0.683	tINS	RR	Clk_ibuf/O
1.554	0.872	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.677	0.678	tINS	FF	Clk_ibuf/O
6.056	0.378	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW8

MPW Summary:

Slack:	3.506
Actual Width:	4.506
Required Width:	1.000
Type:	High Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
0.683	0.683	tINS	RR	Clk_ibuf/O
1.545	0.862	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.677	0.678	tINS	FF	Clk_ibuf/O
6.051	0.373	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW9

MPW Summary:

Slack:	4.230
Actual Width:	4.480
Required Width:	0.250
Type:	Low Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.688	0.688	tINS	FF	Clk_ibuf/O
6.603	0.915	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.675	0.675	tINS	RR	Clk_ibuf/O
11.083	0.407	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK

MPW10

MPW Summary:

Slack:	4.230
Actual Width:	4.480
Required Width:	0.250
Type:	Low Pulse Width
Clock:	Clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.688	0.688	tINS	FF	Clk_ibuf/O
6.603	0.915	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.675	0.675	tINS	RR	Clk_ibuf/O
11.083	0.407	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
335	Clk_d	4.731	0.915
244	control0[0]	2.702	2.369
57	n20_3	43.808	2.355
52	byte_rx_done	6.847	1.699
51	rst_ao	3.434	0.781
43	state[0]	4.926	0.845
41	state[0]	7.254	0.894
38	op_reg_en	41.418	1.090
37	data_out_shift_reg_34_7	41.656	2.364
37	led_d[0]	7.401	3.923

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R20C47	43.06%
R22C41	43.06%
R22C43	43.06%
R18C46	41.67%
R14C45	40.28%
R23C41	40.28%
R22C48	40.28%
R18C48	38.89%
R22C47	38.89%
R21C41	38.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command