Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\download\ch41_ov5640_ddr3_tft\src\camera_init\camera_init.v H:\download\ch41_ov5640_ddr3_tft\src\camera_init\i2c_control\i2c_bit_shift.v H:\download\ch41_ov5640_ddr3_tft\src\camera_init\i2c_control\i2c_control.v H:\download\ch41_ov5640_ddr3_tft\src\camera_init\ov5640_init_table_jpeg.v H:\download\ch41_ov5640_ddr3_tft\src\camera_init\ov5640_init_table_rgb.v H:\download\ch41_ov5640_ddr3_tft\src\camera_pll\camera_pll.v H:\download\ch41_ov5640_ddr3_tft\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v H:\download\ch41_ov5640_ddr3_tft\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v H:\download\ch41_ov5640_ddr3_tft\src\ddr3_memory_interface\ddr3_memory_interface.v H:\download\ch41_ov5640_ddr3_tft\src\ddr_pll\ddr_pll.v H:\download\ch41_ov5640_ddr3_tft\src\DVP_Capture\DVP_Capture.v H:\download\ch41_ov5640_ddr3_tft\src\gowin_ddr\gowin_ddr.v H:\download\ch41_ov5640_ddr3_tft\src\gowin_pll\gowin_pll.v H:\download\ch41_ov5640_ddr3_tft\src\ov5640_ddr3_tft.v H:\download\ch41_ov5640_ddr3_tft\src\pll_mDRP_intf.v H:\download\ch41_ov5640_ddr3_tft\src\rd_data_fifo\rd_data_fifo.v H:\download\ch41_ov5640_ddr3_tft\src\vga\disp_driver.v H:\download\ch41_ov5640_ddr3_tft\src\vga\disp_parameter_cfg.v H:\download\ch41_ov5640_ddr3_tft\src\vga\dvi_encoder.v H:\download\ch41_ov5640_ddr3_tft\src\wr_data_fifo\wr_data_fifo.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Mon Nov 25 10:53:36 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | ov5640_ddr3_tft |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 0.943s, Peak memory usage = 611.789MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 611.789MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 611.789MB Optimizing Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.239s, Peak memory usage = 611.789MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 611.789MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 611.789MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 611.789MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 611.789MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 611.789MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 611.789MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 611.789MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 611.789MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 611.789MB Generate output files: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.313s, Peak memory usage = 611.789MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 611.789MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 91 |
| I/O Buf | 88 |
| IBUF | 13 |
| OBUF | 53 |
| TBUF | 2 |
| IOBUF | 17 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 4188 |
| DFFSE | 2 |
| DFFRE | 479 |
| DFFPE | 81 |
| DFFCE | 3626 |
| LUT | 3304 |
| LUT2 | 552 |
| LUT3 | 1336 |
| LUT4 | 1416 |
| ALU | 206 |
| ALU | 206 |
| INV | 38 |
| INV | 38 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 21 |
| SDPB | 12 |
| SDPX9B | 8 |
| pROM | 1 |
| CLOCK | 6 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| PLLA | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3548(3342 LUT, 206 ALU) / 23040 | 16% |
| Register | 4188 / 23685 | 18% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 4188 / 23685 | 18% |
| BSRAM | 21 / 56 | 38% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk50m | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | ||
| camera_pclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | camera_pclk_ibuf/I | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1981_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1981_s2/O | ||
| Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT0 |
| Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 41.250 | 24.2 | 0.000 | 20.625 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT1 |
| Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 30.000 | 33.3 | 0.000 | 15.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT3 |
| ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.0 | 0.000 | 1.250 | clk50m_ibuf/I | clk50m | ddr_pll/PLLA_inst/CLKOUT2 |
| ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | ddr_pll/PLLA_inst/CLKOUT2 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk50m | 50.000(MHz) | 260.960(MHz) | 6 | TOP |
| 2 | camera_pclk | 100.000(MHz) | 205.973(MHz) | 7 | TOP |
| 3 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | 100.000(MHz) | 1522.071(MHz) | 1 | TOP |
| 4 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | 100.000(MHz) | 1522.071(MHz) | 1 | TOP |
| 5 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | 100.000(MHz) | 1522.071(MHz) | 1 | TOP |
| 6 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | 100.000(MHz) | 1522.071(MHz) | 1 | TOP |
| 7 | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 219.394(MHz) | 6 | TOP |
| 8 | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | 33.333(MHz) | 193.987(MHz) | 8 | TOP |
| 9 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1394.296(MHz) | 1 | TOP |
| 10 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 725.689(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.182 |
| Data Arrival Time | 11.650 |
| Data Required Time | 10.468 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 |
| Launch Clk | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.328 | 0.828 | tCL | RR | 64 | ddr_pll/PLLA_inst/CLKOUT2 |
| 8.628 | 0.300 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 8.978 | 0.350 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.278 | 0.300 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1 |
| 9.728 | 0.450 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT |
| 9.728 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN |
| 9.768 | 0.040 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT |
| 9.768 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN |
| 9.808 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT |
| 9.808 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN |
| 9.848 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT |
| 9.848 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN |
| 9.888 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT |
| 9.888 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN |
| 9.928 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT |
| 9.928 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN |
| 9.968 | 0.040 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT |
| 10.268 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1 |
| 10.681 | 0.413 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F |
| 10.981 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n222_s0/I2 |
| 11.350 | 0.369 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n222_s0/F |
| 11.650 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.254 | 0.254 | tCL | RR | 3933 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.554 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK |
| 10.519 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 | ||
| 10.468 | -0.051 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0 |
| Clock Skew: | -0.274 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.822, 54.846%; route: 1.200, 36.123%; tC2Q: 0.300, 9.031% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 2
Path Summary:| Slack | -1.182 |
| Data Arrival Time | 11.650 |
| Data Required Time | 10.468 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 |
| Launch Clk | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.328 | 0.828 | tCL | RR | 64 | ddr_pll/PLLA_inst/CLKOUT2 |
| 8.628 | 0.300 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 8.978 | 0.350 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.278 | 0.300 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1 |
| 9.728 | 0.450 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT |
| 9.728 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN |
| 9.768 | 0.040 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT |
| 9.768 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN |
| 9.808 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT |
| 9.808 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN |
| 9.848 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT |
| 9.848 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN |
| 9.888 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT |
| 9.888 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN |
| 9.928 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT |
| 9.928 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN |
| 9.968 | 0.040 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT |
| 10.268 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1 |
| 10.681 | 0.413 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F |
| 10.981 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n221_s0/I2 |
| 11.350 | 0.369 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n221_s0/F |
| 11.650 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.254 | 0.254 | tCL | RR | 3933 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.554 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK |
| 10.519 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 | ||
| 10.468 | -0.051 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0 |
| Clock Skew: | -0.274 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.822, 54.846%; route: 1.200, 36.123%; tC2Q: 0.300, 9.031% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 3
Path Summary:| Slack | -1.182 |
| Data Arrival Time | 11.650 |
| Data Required Time | 10.468 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0 |
| Launch Clk | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.328 | 0.828 | tCL | RR | 64 | ddr_pll/PLLA_inst/CLKOUT2 |
| 8.628 | 0.300 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 8.978 | 0.350 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.278 | 0.300 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1 |
| 9.728 | 0.450 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT |
| 9.728 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN |
| 9.768 | 0.040 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT |
| 9.768 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN |
| 9.808 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT |
| 9.808 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN |
| 9.848 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT |
| 9.848 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN |
| 9.888 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT |
| 9.888 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN |
| 9.928 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT |
| 9.928 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN |
| 9.968 | 0.040 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT |
| 10.268 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1 |
| 10.681 | 0.413 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F |
| 10.981 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2 |
| 11.350 | 0.369 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F |
| 11.650 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.254 | 0.254 | tCL | RR | 3933 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.554 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK |
| 10.519 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0 | ||
| 10.468 | -0.051 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0 |
| Clock Skew: | -0.274 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.822, 54.846%; route: 1.200, 36.123%; tC2Q: 0.300, 9.031% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 4
Path Summary:| Slack | -1.182 |
| Data Arrival Time | 11.650 |
| Data Required Time | 10.468 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0 |
| Launch Clk | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.328 | 0.828 | tCL | RR | 64 | ddr_pll/PLLA_inst/CLKOUT2 |
| 8.628 | 0.300 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 8.978 | 0.350 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.278 | 0.300 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1 |
| 9.728 | 0.450 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT |
| 9.728 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN |
| 9.768 | 0.040 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT |
| 9.768 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN |
| 9.808 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT |
| 9.808 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN |
| 9.848 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT |
| 9.848 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN |
| 9.888 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT |
| 9.888 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN |
| 9.928 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT |
| 9.928 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN |
| 9.968 | 0.040 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT |
| 10.268 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1 |
| 10.681 | 0.413 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F |
| 10.981 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2 |
| 11.350 | 0.369 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F |
| 11.650 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.254 | 0.254 | tCL | RR | 3933 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.554 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK |
| 10.519 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0 | ||
| 10.468 | -0.051 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0 |
| Clock Skew: | -0.274 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.822, 54.846%; route: 1.200, 36.123%; tC2Q: 0.300, 9.031% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 5
Path Summary:| Slack | -1.182 |
| Data Arrival Time | 11.650 |
| Data Required Time | 10.468 |
| From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll |
| To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0 |
| Launch Clk | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.500 | 0.000 | ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 8.328 | 0.828 | tCL | RR | 64 | ddr_pll/PLLA_inst/CLKOUT2 |
| 8.628 | 0.300 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
| 8.978 | 0.350 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
| 9.278 | 0.300 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1 |
| 9.728 | 0.450 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT |
| 9.728 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN |
| 9.768 | 0.040 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT |
| 9.768 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN |
| 9.808 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT |
| 9.808 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN |
| 9.848 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT |
| 9.848 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN |
| 9.888 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT |
| 9.888 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN |
| 9.928 | 0.040 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT |
| 9.928 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN |
| 9.968 | 0.040 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT |
| 10.268 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1 |
| 10.681 | 0.413 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F |
| 10.981 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I2 |
| 11.350 | 0.369 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F |
| 11.650 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.254 | 0.254 | tCL | RR | 3933 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.554 | 0.300 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK |
| 10.519 | -0.035 | tUnc | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0 | ||
| 10.468 | -0.051 | tSu | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0 |
| Clock Skew: | -0.274 |
| Setup Relationship: | 2.500 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.822, 54.846%; route: 1.200, 36.123%; tC2Q: 0.300, 9.031% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |