Timing Messages

Report Title	Timing Analysis Report
Design File	H:\download\ch41_ov5640_ddr3_tft\impl\gwsynthesis\ov5640_ddr3_tft.vg
Physical Constraints File	H:\download\ch41_ov5640_ddr3_tft\src\ov5640_ddr3_tft.cst
Timing Constraint File	---
Tool Version	V1.9.9.01 (64-bit)
Part Number	GW5A-LV25UG324C2/I1
Device	GW5A-25
Device Version	A
Created Time	Mon Nov 25 10:53:54 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	20892
Numbers of Endpoints Analyzed	14593
Numbers of Falling Endpoints	62
Numbers of Setup Violated Endpoints	91
Numbers of Hold Violated Endpoints	21

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk50m	Base	20.000	50.000	0.000	10.000			clk50m_ibuf/I
camera_pclk	Base	10.000	100.000	0.000	5.000			camera_pclk_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Generated	20.000	50.000	0.000	10.000	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Generated	41.250	24.242	0.000	20.625	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT1
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk	Generated	30.000	33.333	0.000	15.000	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT3
ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk	Generated	2.500	400.000	0.000	1.250	clk50m_ibuf/I	clk50m	ddr_pll/PLLA_inst/CLKOUT2
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Generated	10.000	100.000	0.000	5.000	ddr_pll/PLLA_inst/CLKOUT2	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk50m	50.000(MHz)	278.087(MHz)	6	TOP
2	camera_pclk	100.000(MHz)	177.148(MHz)	7	TOP
3	Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	50.000(MHz)	194.363(MHz)	5	TOP
4	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk	33.333(MHz)	107.150(MHz)	8	TOP
5	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk	400.000(MHz)	2338.898(MHz)	1	TOP
6	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	100.000(MHz)	251.414(MHz)	2	TOP

No timing paths to get frequency of Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk50m	Setup	0.000	0
clk50m	Hold	0.000	0
camera_pclk	Setup	0.000	0
camera_pclk	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk	Hold	0.000	0
ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk	Setup	0.000	0
ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk	Hold	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Setup	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-3.772	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.807
2	-3.699	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.386	5.727
3	-3.690	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.725
4	-3.632	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.667
5	-3.578	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.613
6	-3.481	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.516
7	-3.459	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.405	5.468
8	-3.174	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.209
9	-2.978	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.379	5.013
10	-2.870	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.386	4.898
11	-2.766	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	-0.363	3.927
12	-2.233	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	-0.363	3.394
13	-2.022	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_5_s1/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.390	4.046
14	-2.015	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_0_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.404	4.026
15	-1.987	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.404	3.998
16	-1.951	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.406	3.959
17	-1.831	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_1_s1/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.390	3.855
18	-1.827	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.406	3.835
19	-1.784	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_6_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.406	3.792
20	-1.770	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.406	3.778
21	-1.752	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_1_s0/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.406	3.760
22	-1.742	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_0_s1/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.390	3.766
23	-1.729	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1/D	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	2.500	0.398	3.745
24	6.023	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	-0.001	3.927
25	6.556	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	-0.001	3.394

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.633	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_5_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.096	0.479
2	-0.627	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_2_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.096	0.485
3	-0.619	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_7_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.082	0.479
4	-0.556	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.100	0.560
5	-0.548	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_3_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.086	0.554
6	-0.542	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_4_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.086	0.560
7	-0.527	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_1_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.092	0.581
8	-0.516	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_8_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.090	0.590
9	-0.464	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.927	0.479
10	-0.461	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_6_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.097	0.652
11	-0.460	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.923	0.479
12	-0.460	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.923	0.479
13	-0.456	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.919	0.479
14	-0.456	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.919	0.479
15	-0.423	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_9_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]	0.000	-1.098	0.691
16	-0.385	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.923	0.554
17	-0.382	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.926	0.560
18	-0.374	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.924	0.566
19	-0.365	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.924	0.575
20	-0.357	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	camera_pclk:[R]	0.000	-0.924	0.583
21	-0.256	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_1_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/D	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	clk50m:[R]	0.000	-0.580	0.360
22	0.109	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[22]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.006	0.318
23	0.109	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[21]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.006	0.318
24	0.109	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.006	0.318
25	0.126	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_99_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[27]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.021	0.320

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.167	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
2	-1.167	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
3	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
4	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
5	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
6	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
7	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
8	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
9	-0.878	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	1.250	0.208	1.754
10	0.081	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
11	0.081	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
12	0.370	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
13	0.370	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
14	0.370	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
15	0.370	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
16	0.370	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
17	0.370	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	2.500	0.208	1.754
18	7.210	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.571	1.754
19	7.210	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.571	1.754
20	7.500	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.579	1.754
21	7.508	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.571	1.754
22	7.508	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.571	1.754
23	7.508	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.571	1.754
24	7.508	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.571	1.754
25	7.515	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	10.000	0.564	1.754

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.153	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.516	0.836
2	0.153	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.516	0.836
3	0.230	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.439	0.836
4	0.230	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.439	0.836
5	0.230	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.439	0.836
6	0.230	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.439	0.836
7	0.230	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.439	0.836
8	0.470	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.198	0.836
9	0.470	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.198	0.836
10	0.470	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.198	0.836
11	0.470	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.198	0.836
12	0.470	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.198	0.836
13	0.470	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]	0.000	-0.198	0.836
14	1.233	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.564	0.836
15	1.237	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.568	0.836
16	1.237	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.568	0.836
17	1.237	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.568	0.836
18	1.241	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.572	0.836
19	1.241	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.572	0.836
20	1.387	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	-1.250	-0.534	0.836
21	1.387	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	-1.250	-0.534	0.836
22	1.473	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	-1.250	-0.448	0.836
23	1.473	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	-1.250	-0.448	0.836
24	1.473	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	-1.250	-0.448	0.836
25	1.473	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]	-1.250	-0.448	0.836

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.455	4.317	0.862	High Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s
2	3.455	4.317	0.862	High Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s
3	3.458	4.320	0.862	High Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s
4	3.458	4.320	0.862	High Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s
5	3.479	4.341	0.862	Low Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s
6	3.479	4.341	0.862	Low Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s
7	3.482	4.344	0.862	Low Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s
8	3.482	4.344	0.862	Low Pulse Width	camera_pclk	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s
9	3.737	4.599	0.862	Low Pulse Width	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s
10	3.737	4.599	0.862	Low Pulse Width	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-3.772
Data Arrival Time	14.394
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.290	2.646	tNET	RR	2	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/I0
12.735	0.445	tINS	RF	1	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/COUT
12.735	0.000	tNET	FF	2	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/CIN
12.775	0.040	tINS	FR	1	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/COUT
12.775	0.000	tNET	RR	2	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/CIN
12.815	0.040	tINS	RR	1	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/COUT
12.815	0.000	tNET	RR	2	R29C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n209_s/CIN
13.052	0.237	tINS	RR	1	R29C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n209_s/SUM
13.973	0.921	tNET	RR	1	R27C31[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/I1
14.394	0.421	tINS	RR	1	R27C31[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/F
14.394	0.000	tNET	RR	1	R27C31[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
10.623	-0.051	tSu		1	R27C31[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.533, 26.400%; route: 3.567, 61.429%; tC2Q: 0.707, 12.171%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path2

Path Summary:

Slack	-3.699
Data Arrival Time	14.314
Data Required Time	10.615
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.290	2.646	tNET	RR	2	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/I0
12.735	0.445	tINS	RF	1	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/COUT
12.735	0.000	tNET	FF	2	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/CIN
12.775	0.040	tINS	FR	1	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/COUT
12.775	0.000	tNET	RR	2	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/CIN
12.815	0.040	tINS	RR	1	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/COUT
12.815	0.000	tNET	RR	2	R29C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n209_s/CIN
12.855	0.040	tINS	RR	1	R29C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n209_s/COUT
12.855	0.000	tNET	RR	2	R29C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/CIN
12.895	0.040	tINS	RR	1	R29C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/COUT
12.895	0.000	tNET	RR	2	R29C27[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n207_s/CIN
13.132	0.237	tINS	RR	1	R29C27[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n207_s/SUM
13.901	0.769	tNET	RR	1	R27C30[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/I1
14.314	0.413	tINS	RR	1	R27C30[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/F
14.314	0.000	tNET	RR	1	R27C30[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.701	0.701	tNET	RR	1	R27C30[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/CLK
10.666	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
10.615	-0.051	tSu		1	R27C30[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0

Path Statistics:

Clock Skew	-0.386
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.605, 28.026%; route: 3.415, 59.633%; tC2Q: 0.707, 12.341%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path3

Path Summary:

Slack	-3.690
Data Arrival Time	14.312
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.290	2.646	tNET	RR	2	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/I0
12.735	0.445	tINS	RF	1	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/COUT
12.735	0.000	tNET	FF	2	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/CIN
12.775	0.040	tINS	FR	1	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/COUT
12.775	0.000	tNET	RR	2	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/CIN
12.970	0.195	tINS	RR	1	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/SUM
13.891	0.921	tNET	RR	1	R27C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I1
14.312	0.421	tINS	RR	1	R27C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F
14.312	0.000	tNET	RR	1	R27C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
10.623	-0.051	tSu		1	R27C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.451, 25.346%; route: 3.567, 62.309%; tC2Q: 0.707, 12.346%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path4

Path Summary:

Slack	-3.632
Data Arrival Time	14.254
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.290	2.646	tNET	RR	2	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/I0
12.735	0.445	tINS	RF	1	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/COUT
12.735	0.000	tNET	FF	2	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/CIN
12.775	0.040	tINS	FR	1	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/COUT
12.775	0.000	tNET	RR	2	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/CIN
12.815	0.040	tINS	RR	1	R29C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n210_s/COUT
12.815	0.000	tNET	RR	2	R29C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n209_s/CIN
12.855	0.040	tINS	RR	1	R29C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n209_s/COUT
12.855	0.000	tNET	RR	2	R29C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/CIN
13.050	0.195	tINS	RR	1	R29C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/SUM
13.841	0.791	tNET	RR	1	R27C31[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/I1
14.254	0.413	tINS	RR	1	R27C31[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/F
14.254	0.000	tNET	RR	1	R27C31[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
10.623	-0.051	tSu		1	R27C31[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.523, 26.876%; route: 3.437, 60.652%; tC2Q: 0.707, 12.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path5

Path Summary:

Slack	-3.578
Data Arrival Time	14.200
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.290	2.646	tNET	RR	2	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/I0
12.735	0.445	tINS	RF	1	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/COUT
12.735	0.000	tNET	FF	2	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/CIN
12.972	0.237	tINS	FR	1	R29C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n211_s/SUM
13.779	0.807	tNET	RR	1	R27C31[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I1
14.200	0.421	tINS	RR	1	R27C31[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F
14.200	0.000	tNET	RR	1	R27C31[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
10.623	-0.051	tSu		1	R27C31[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.453, 25.887%; route: 3.453, 61.521%; tC2Q: 0.707, 12.592%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path6

Path Summary:

Slack	-3.481
Data Arrival Time	14.103
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.290	2.646	tNET	RR	2	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/I0
12.875	0.585	tINS	RR	1	R29C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n212_s/SUM
13.682	0.807	tNET	RR	1	R27C31[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I1
14.103	0.421	tINS	RR	1	R27C31[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F
14.103	0.000	tNET	RR	1	R27C31[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
10.623	-0.051	tSu		1	R27C31[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.356, 24.584%; route: 3.453, 62.603%; tC2Q: 0.707, 12.813%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path7

Path Summary:

Slack	-3.459
Data Arrival Time	14.055
Data Required Time	10.596
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.444	2.800	tNET	RR	2	R30C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s18/I0
12.889	0.445	tINS	RF	1	R30C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s18/COUT
12.889	0.000	tNET	FF	2	R30C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s19/CIN
12.929	0.040	tINS	FR	1	R30C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s19/COUT
12.929	0.000	tNET	RR	2	R30C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s20/CIN
12.969	0.040	tINS	RR	1	R30C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s20/COUT
12.969	0.000	tNET	RR	2	R30C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s21/CIN
13.009	0.040	tINS	RR	1	R30C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s21/COUT
13.009	0.000	tNET	RR	2	R30C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s22/CIN
13.049	0.040	tINS	RR	1	R30C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s22/COUT
13.049	0.000	tNET	RR	2	R30C27[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s23/CIN
13.089	0.040	tINS	RR	1	R30C27[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s23/COUT
13.686	0.597	tNET	RR	1	R29C29[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n249_s2/I0
14.055	0.369	tINS	RR	1	R29C29[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n249_s2/F
14.055	0.000	tNET	RR	1	R29C29[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.682	0.682	tNET	RR	1	R29C29[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/CLK
10.647	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
10.596	-0.051	tSu		1	R29C29[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0

Path Statistics:

Clock Skew	-0.405
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.364, 24.946%; route: 3.397, 62.128%; tC2Q: 0.707, 12.926%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path8

Path Summary:

Slack	-3.174
Data Arrival Time	13.796
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.097	2.453	tNET	RR	2	R29C26[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s/I0
12.542	0.445	tINS	RF	1	R29C26[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s/COUT
12.542	0.000	tNET	FF	2	R29C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s/CIN
12.779	0.237	tINS	FR	1	R29C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s/SUM
13.586	0.807	tNET	RR	1	R27C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n221_s0/I1
13.796	0.210	tINS	RR	1	R27C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n221_s0/F
13.796	0.000	tNET	RR	1	R27C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
10.623	-0.051	tSu		1	R27C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.242, 23.844%; route: 3.260, 62.587%; tC2Q: 0.707, 13.569%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path9

Path Summary:

Slack	-2.978
Data Arrival Time	13.600
Data Required Time	10.622
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
11.552	1.908	tNET	RR	2	R27C26[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1
11.946	0.394	tINS	RR	1	R27C26[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT
11.946	0.000	tNET	RR	2	R27C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN
11.986	0.040	tINS	RR	1	R27C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT
11.986	0.000	tNET	RR	2	R27C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN
12.026	0.040	tINS	RR	1	R27C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT
12.026	0.000	tNET	RR	2	R27C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN
12.066	0.040	tINS	RR	1	R27C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT
12.066	0.000	tNET	RR	2	R27C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN
12.106	0.040	tINS	RR	1	R27C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT
12.106	0.000	tNET	RR	2	R27C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN
12.146	0.040	tINS	RR	1	R27C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT
12.146	0.000	tNET	RR	2	R27C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN
12.186	0.040	tINS	RF	2	R27C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT
12.569	0.383	tNET	FF	1	R27C29[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1
12.986	0.417	tINS	FR	9	R27C29[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F
13.600	0.614	tNET	RR	1	R27C31[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.708	0.709	tNET	RR	1	R27C31[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/CLK
10.674	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
10.623	-0.051	tSu		1	R27C31[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0

Path Statistics:

Clock Skew	-0.379
Setup Relationship	2.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.401, 27.948%; route: 2.905, 57.953%; tC2Q: 0.707, 14.099%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path10

Path Summary:

Slack	-2.870
Data Arrival Time	13.485
Data Required Time	10.615
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
11.552	1.908	tNET	RR	2	R27C26[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/I1
11.946	0.394	tINS	RR	1	R27C26[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s16/COUT
11.946	0.000	tNET	RR	2	R27C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/CIN
11.986	0.040	tINS	RR	1	R27C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s17/COUT
11.986	0.000	tNET	RR	2	R27C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/CIN
12.026	0.040	tINS	RR	1	R27C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s18/COUT
12.026	0.000	tNET	RR	2	R27C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/CIN
12.066	0.040	tINS	RR	1	R27C26[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s19/COUT
12.066	0.000	tNET	RR	2	R27C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/CIN
12.106	0.040	tINS	RR	1	R27C26[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s20/COUT
12.106	0.000	tNET	RR	2	R27C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/CIN
12.146	0.040	tINS	RR	1	R27C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s21/COUT
12.146	0.000	tNET	RR	2	R27C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/CIN
12.186	0.040	tINS	RF	2	R27C27[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n180_s22/COUT
12.569	0.383	tNET	FF	1	R27C29[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/I1
12.986	0.417	tINS	FR	9	R27C29[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n252_s1/F
13.116	0.130	tNET	RR	1	R27C30[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n222_s0/I2
13.485	0.369	tINS	RR	1	R27C30[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n222_s0/F
13.485	0.000	tNET	RR	1	R27C30[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.701	0.701	tNET	RR	1	R27C30[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK
10.666	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
10.615	-0.051	tSu		1	R27C30[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0

Path Statistics:

Clock Skew	-0.386
Setup Relationship	2.500
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.770, 36.139%; route: 2.421, 49.431%; tC2Q: 0.707, 14.430%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path11

Path Summary:

Slack	-2.766
Data Arrival Time	4.651
Data Required Time	1.885
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R23C39[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
1.030	0.306	tC2Q	RR	12	R23C39[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.318	0.288	tNET	RR	1	R24C40[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
1.716	0.398	tINS	RR	1	R24C40[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
4.651	2.935	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.885	-0.417	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.363
Setup Relationship	1.250
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.398, 10.135%; route: 3.223, 82.073%; tC2Q: 0.306, 7.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	-2.233
Data Arrival Time	4.118
Data Required Time	1.885
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R23C39[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
1.030	0.306	tC2Q	RR	12	R23C39[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.320	0.290	tNET	RR	1	R24C38[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
1.689	0.369	tINS	RR	1	R24C38[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
4.118	2.429	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.885	-0.417	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.363
Setup Relationship	1.250
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.369, 10.872%; route: 2.719, 80.112%; tC2Q: 0.306, 9.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	-2.022
Data Arrival Time	12.633
Data Required Time	10.611
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_5_s1
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[5]
12.212	2.568	tNET	RR	1	R29C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n151_s0/I0
12.633	0.421	tINS	RR	1	R29C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n151_s0/F
12.633	0.000	tNET	RR	1	R29C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.697	0.697	tNET	RR	1	R29C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_5_s1/CLK
10.662	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_5_s1
10.611	-0.051	tSu		1	R29C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_5_s1

Path Statistics:

Clock Skew	-0.390
Setup Relationship	2.500
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.771, 19.056%; route: 2.568, 63.474%; tC2Q: 0.707, 17.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Path14

Path Summary:

Slack	-2.015
Data Arrival Time	12.613
Data Required Time	10.598
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_0_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.613	2.969	tNET	RR	1	R30C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.684	0.684	tNET	RR	1	R30C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_0_s0/CLK
10.649	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_0_s0
10.598	-0.051	tSu		1	R30C27[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_0_s0

Path Statistics:

Clock Skew	-0.404
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 8.693%; route: 2.969, 73.751%; tC2Q: 0.707, 17.556%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%

Path15

Path Summary:

Slack	-1.987
Data Arrival Time	12.585
Data Required Time	10.598
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[3]
12.585	2.941	tNET	RR	1	R30C27[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.684	0.684	tNET	RR	1	R30C27[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0/CLK
10.649	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0
10.598	-0.051	tSu		1	R30C27[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_3_s0

Path Statistics:

Clock Skew	-0.404
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 8.754%; route: 2.941, 73.567%; tC2Q: 0.707, 17.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%

Path16

Path Summary:

Slack	-1.951
Data Arrival Time	12.546
Data Required Time	10.595
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
12.546	2.902	tNET	RR	1	R31C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.681	0.681	tNET	RR	1	R31C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/CLK
10.646	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0
10.595	-0.051	tSu		1	R31C26[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_2_s0

Path Statistics:

Clock Skew	-0.406
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 8.841%; route: 2.902, 73.306%; tC2Q: 0.707, 17.853%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path17

Path Summary:

Slack	-1.831
Data Arrival Time	12.442
Data Required Time	10.611
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_1_s1
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[1]
12.029	2.385	tNET	RR	1	R29C27[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n155_s0/I0
12.442	0.413	tINS	RR	1	R29C27[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n155_s0/F
12.442	0.000	tNET	RR	1	R29C27[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.697	0.697	tNET	RR	1	R29C27[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_1_s1/CLK
10.662	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_1_s1
10.611	-0.051	tSu		1	R29C27[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_1_s1

Path Statistics:

Clock Skew	-0.390
Setup Relationship	2.500
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.763, 19.793%; route: 2.385, 61.872%; tC2Q: 0.707, 18.335%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Path18

Path Summary:

Slack	-1.827
Data Arrival Time	12.422
Data Required Time	10.595
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[5]
12.422	2.778	tNET	RR	1	R31C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.681	0.681	tNET	RR	1	R31C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/CLK
10.646	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0
10.595	-0.051	tSu		1	R31C26[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_5_s0

Path Statistics:

Clock Skew	-0.406
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 9.126%; route: 2.778, 72.443%; tC2Q: 0.707, 18.430%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path19

Path Summary:

Slack	-1.784
Data Arrival Time	12.379
Data Required Time	10.595
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_6_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[6]
12.379	2.735	tNET	RR	1	R31C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.681	0.681	tNET	RR	1	R31C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_6_s0/CLK
10.646	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_6_s0
10.595	-0.051	tSu		1	R31C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_6_s0

Path Statistics:

Clock Skew	-0.406
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 9.230%; route: 2.735, 72.131%; tC2Q: 0.707, 18.639%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path20

Path Summary:

Slack	-1.770
Data Arrival Time	12.365
Data Required Time	10.595
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	9	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[7]
12.365	2.721	tNET	RR	1	R31C26[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.681	0.681	tNET	RR	1	R31C26[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/CLK
10.646	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0
10.595	-0.051	tSu		1	R31C26[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_7_s0

Path Statistics:

Clock Skew	-0.406
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 9.264%; route: 2.721, 72.028%; tC2Q: 0.707, 18.708%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path21

Path Summary:

Slack	-1.752
Data Arrival Time	12.347
Data Required Time	10.595
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_1_s0
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[1]
12.347	2.703	tNET	RR	1	R31C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.681	0.681	tNET	RR	1	R31C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_1_s0/CLK
10.646	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_1_s0
10.595	-0.051	tSu		1	R31C26[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/dll_step_base_1_s0

Path Statistics:

Clock Skew	-0.406
Setup Relationship	2.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.350, 9.308%; route: 2.703, 71.894%; tC2Q: 0.707, 18.798%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path22

Path Summary:

Slack	-1.742
Data Arrival Time	12.353
Data Required Time	10.611
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_0_s1
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.143	2.499	tNET	RR	1	R29C27[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n156_s0/I0
12.353	0.210	tINS	RR	1	R29C27[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n156_s0/F
12.353	0.000	tNET	RR	1	R29C27[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.697	0.697	tNET	RR	1	R29C27[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_0_s1/CLK
10.662	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_0_s1
10.611	-0.051	tSu		1	R29C27[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_0_s1

Path Statistics:

Clock Skew	-0.390
Setup Relationship	2.500
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.560, 14.870%; route: 2.499, 66.362%; tC2Q: 0.707, 18.768%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Path23

Path Summary:

Slack	-1.729
Data Arrival Time	12.332
Data Required Time	10.603
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1
Launch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
8.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
9.294	0.707	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
9.644	0.350	tINS	RR	9	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[7]
12.000	2.356	tNET	RR	1	R29C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n149_s0/I0
12.332	0.332	tINS	RR	1	R29C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n149_s0/F
12.332	0.000	tNET	RR	1	R29C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.689	0.689	tNET	RR	1	R29C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1/CLK
10.655	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1
10.604	-0.051	tSu		1	R29C26[3][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/pre_dllstep_7_s1

Path Statistics:

Clock Skew	-0.398
Setup Relationship	2.500
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.682, 18.212%; route: 2.356, 62.915%; tC2Q: 0.707, 18.873%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path24

Path Summary:

Slack	6.023
Data Arrival Time	4.651
Data Required Time	10.674
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R23C39[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
1.030	0.306	tC2Q	RR	12	R23C39[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.318	0.288	tNET	RR	1	R24C40[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
1.716	0.398	tINS	RR	1	R24C40[3][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
4.651	2.935	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
10.674	-0.051	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.398, 10.135%; route: 3.223, 82.073%; tC2Q: 0.306, 7.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path25

Path Summary:

Slack	6.556
Data Arrival Time	4.118
Data Required Time	10.674
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.724	0.724	tNET	RR	1	R23C39[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
1.030	0.306	tC2Q	RR	12	R23C39[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.320	0.290	tNET	RR	1	R24C38[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
1.689	0.369	tINS	RR	1	R24C38[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
4.118	2.429	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
10.674	-0.051	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay	cell: 0.369, 10.872%; route: 2.719, 80.112%; tC2Q: 0.306, 9.016%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.633
Data Arrival Time	30.783
Data Required Time	31.416
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_5_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.304	0.304	tNET	RR	1	R27C63[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/CLK
30.448	0.144	tC2Q	RR	1	R27C63[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/Q
30.783	0.335	tNET	RR	1	R26C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.400	0.305	tNET	RR	1	R26C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_5_s0/CLK
31.435	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_5_s0
31.416	-0.019	tHld		1	R26C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_5_s0

Path Statistics:

Clock Skew	1.096
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.304, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.305, 100.000%

Path2

Path Summary:

Slack	-0.627
Data Arrival Time	30.785
Data Required Time	31.412
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_2_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.300	0.300	tNET	RR	1	R27C64[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/CLK
30.444	0.144	tC2Q	RR	1	R27C64[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/Q
30.785	0.341	tNET	RR	1	R26C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.396	0.301	tNET	RR	1	R26C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_2_s0/CLK
31.431	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_2_s0
31.412	-0.019	tHld		1	R26C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_2_s0

Path Statistics:

Clock Skew	1.096
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.341, 70.309%; tC2Q: 0.144, 29.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%

Path3

Path Summary:

Slack	-0.619
Data Arrival Time	30.788
Data Required Time	31.407
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_7_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.309	0.309	tNET	RR	1	R26C63[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/CLK
30.453	0.144	tC2Q	RR	1	R26C63[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/Q
30.788	0.335	tNET	RR	1	R27C62[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.391	0.296	tNET	RR	1	R27C62[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_7_s0/CLK
31.426	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_7_s0
31.407	-0.019	tHld		1	R27C62[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_7_s0

Path Statistics:

Clock Skew	1.082
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.309, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.296, 100.000%

Path4

Path Summary:

Slack	-0.556
Data Arrival Time	30.865
Data Required Time	31.421
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.305	0.305	tNET	RR	1	R26C64[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/CLK
30.449	0.144	tC2Q	RR	1	R26C64[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q
30.865	0.416	tNET	RR	1	R25C63[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.405	0.310	tNET	RR	1	R25C63[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s0/CLK
31.440	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s0
31.421	-0.019	tHld		1	R25C63[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s0

Path Statistics:

Clock Skew	1.100
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.305, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.416, 74.286%; tC2Q: 0.144, 25.714%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.310, 100.000%

Path5

Path Summary:

Slack	-0.548
Data Arrival Time	30.863
Data Required Time	31.411
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_3_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.309	0.309	tNET	RR	1	R26C63[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/CLK
30.453	0.144	tC2Q	RR	1	R26C63[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q
30.863	0.410	tNET	RR	1	R27C61[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.395	0.300	tNET	RR	1	R27C61[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_3_s0/CLK
31.430	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_3_s0
31.411	-0.019	tHld		1	R27C61[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_3_s0

Path Statistics:

Clock Skew	1.086
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.309, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 74.007%; tC2Q: 0.144, 25.993%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.300, 100.000%

Path6

Path Summary:

Slack	-0.542
Data Arrival Time	30.869
Data Required Time	31.411
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_4_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.309	0.309	tNET	RR	1	R26C63[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/CLK
30.453	0.144	tC2Q	RR	1	R26C63[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/Q
30.869	0.416	tNET	RR	1	R27C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.395	0.300	tNET	RR	1	R27C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_4_s0/CLK
31.430	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_4_s0
31.411	-0.019	tHld		1	R27C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_4_s0

Path Statistics:

Clock Skew	1.086
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.309, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.416, 74.286%; tC2Q: 0.144, 25.714%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.300, 100.000%

Path7

Path Summary:

Slack	-0.527
Data Arrival Time	30.885
Data Required Time	31.412
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_1_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.304	0.304	tNET	RR	1	R27C63[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/CLK
30.448	0.144	tC2Q	RR	1	R27C63[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/Q
30.885	0.437	tNET	RR	1	R26C62[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.396	0.301	tNET	RR	1	R26C62[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_1_s0/CLK
31.431	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_1_s0
31.412	-0.019	tHld		1	R26C62[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_1_s0

Path Statistics:

Clock Skew	1.092
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.304, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.437, 75.215%; tC2Q: 0.144, 24.785%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%

Path8

Path Summary:

Slack	-0.516
Data Arrival Time	30.891
Data Required Time	31.407
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_8_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.301	0.301	tNET	RR	1	R26C65[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/CLK
30.445	0.144	tC2Q	RR	1	R26C65[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q
30.891	0.446	tNET	RR	1	R27C62[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.391	0.296	tNET	RR	1	R27C62[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_8_s0/CLK
31.426	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_8_s0
31.407	-0.019	tHld		1	R27C62[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_8_s0

Path Statistics:

Clock Skew	1.090
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.446, 75.593%; tC2Q: 0.144, 24.407%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.296, 100.000%

Path9

Path Summary:

Slack	-0.464
Data Arrival Time	0.792
Data Required Time	1.256
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.313	0.313	tNET	RR	1	R21C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0/CLK
0.457	0.144	tC2Q	RR	1	R21C61[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0/Q
0.792	0.335	tNET	RR	1	R22C60[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.240	0.659	tNET	RR	1	R22C60[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0/CLK
1.275	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0
1.256	-0.019	tHld		1	R22C60[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0

Path Statistics:

Clock Skew	0.927
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.313, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.581, 46.842%; route: 0.659, 53.158%

Path10

Path Summary:

Slack	-0.461
Data Arrival Time	30.946
Data Required Time	31.407
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_6_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.294	0.294	tNET	RR	1	R29C63[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/CLK
30.438	0.144	tC2Q	RR	1	R29C63[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/Q
30.946	0.508	tNET	RR	1	R27C62[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.391	0.296	tNET	RR	1	R27C62[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_6_s0/CLK
31.426	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_6_s0
31.407	-0.019	tHld		1	R27C62[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_6_s0

Path Statistics:

Clock Skew	1.097
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.508, 77.914%; tC2Q: 0.144, 22.086%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.296, 100.000%

Path11

Path Summary:

Slack	-0.460
Data Arrival Time	0.791
Data Required Time	1.251
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.312	0.312	tNET	RR	1	R24C60[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/CLK
0.456	0.144	tC2Q	RR	1	R24C60[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/Q
0.791	0.335	tNET	RR	1	R25C62[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.235	0.654	tNET	RR	1	R25C62[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/CLK
1.270	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0
1.251	-0.019	tHld		1	R25C62[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0

Path Statistics:

Clock Skew	0.923
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.312, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.581, 47.042%; route: 0.654, 52.958%

Path12

Path Summary:

Slack	-0.460
Data Arrival Time	0.791
Data Required Time	1.251
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.312	0.312	tNET	RR	1	R24C60[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/CLK
0.456	0.144	tC2Q	RR	1	R24C60[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/Q
0.791	0.335	tNET	RR	1	R25C62[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.235	0.654	tNET	RR	1	R25C62[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/CLK
1.270	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0
1.251	-0.019	tHld		1	R25C62[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0

Path Statistics:

Clock Skew	0.923
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.312, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.581, 47.042%; route: 0.654, 52.958%

Path13

Path Summary:

Slack	-0.456
Data Arrival Time	0.794
Data Required Time	1.250
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.315	0.315	tNET	RR	1	R22C60[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0/CLK
0.459	0.144	tC2Q	RR	1	R22C60[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0/Q
0.794	0.335	tNET	RR	1	R23C59[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.234	0.654	tNET	RR	1	R23C59[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0/CLK
1.269	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0
1.250	-0.019	tHld		1	R23C59[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0

Path Statistics:

Clock Skew	0.919
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.581, 47.061%; route: 0.654, 52.939%

Path14

Path Summary:

Slack	-0.456
Data Arrival Time	0.794
Data Required Time	1.250
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.315	0.315	tNET	RR	1	R22C60[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0/CLK
0.459	0.144	tC2Q	RR	1	R22C60[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0/Q
0.794	0.335	tNET	RR	1	R23C59[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.234	0.654	tNET	RR	1	R23C59[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0/CLK
1.269	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0
1.250	-0.019	tHld		1	R23C59[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0

Path Statistics:

Clock Skew	0.919
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.335, 69.937%; tC2Q: 0.144, 30.063%
Required Clock Path Delay	cell: 0.581, 47.061%; route: 0.654, 52.939%

Path15

Path Summary:

Slack	-0.423
Data Arrival Time	30.997
Data Required Time	31.420
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_9_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
30.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
30.306	0.306	tNET	RR	1	R25C65[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/CLK
30.450	0.144	tC2Q	RR	3	R25C65[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/Q
30.997	0.547	tNET	RR	1	R23C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
31.095	1.095	tCL	RR	90	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT3
31.404	0.309	tNET	RR	1	R23C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_9_s0/CLK
31.439	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_9_s0
31.420	-0.019	tHld		1	R23C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_9_s0

Path Statistics:

Clock Skew	1.098
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.306, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.547, 79.161%; tC2Q: 0.144, 20.839%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.309, 100.000%

Path16

Path Summary:

Slack	-0.385
Data Arrival Time	0.866
Data Required Time	1.251
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.312	0.312	tNET	RR	1	R24C60[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0/CLK
0.456	0.144	tC2Q	RR	1	R24C60[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0/Q
0.866	0.410	tNET	RR	1	R25C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.235	0.654	tNET	RR	1	R25C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0/CLK
1.270	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0
1.251	-0.019	tHld		1	R25C62[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0

Path Statistics:

Clock Skew	0.923
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.312, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 74.007%; tC2Q: 0.144, 25.993%
Required Clock Path Delay	cell: 0.581, 47.042%; route: 0.654, 52.958%

Path17

Path Summary:

Slack	-0.382
Data Arrival Time	0.873
Data Required Time	1.255
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.313	0.313	tNET	RR	1	R21C61[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0/CLK
0.457	0.144	tC2Q	RR	1	R21C61[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0/Q
0.873	0.416	tNET	RR	1	R25C61[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.239	0.658	tNET	RR	1	R25C61[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0/CLK
1.274	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0
1.255	-0.019	tHld		1	R25C61[1][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0

Path Statistics:

Clock Skew	0.926
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.313, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.416, 74.286%; tC2Q: 0.144, 25.714%
Required Clock Path Delay	cell: 0.581, 46.890%; route: 0.658, 53.110%

Path18

Path Summary:

Slack	-0.374
Data Arrival Time	0.857
Data Required Time	1.231
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.292	0.292	tNET	RR	1	R17C61[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0/CLK
0.435	0.144	tC2Q	RR	4	R17C61[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0/Q
0.857	0.422	tNET	RR	1	R16C59[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.215	0.634	tNET	RR	1	R16C59[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0/CLK
1.250	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0
1.231	-0.019	tHld		1	R16C59[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0

Path Statistics:

Clock Skew	0.924
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 74.558%; tC2Q: 0.144, 25.442%
Required Clock Path Delay	cell: 0.581, 47.806%; route: 0.634, 52.194%

Path19

Path Summary:

Slack	-0.365
Data Arrival Time	0.890
Data Required Time	1.255
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.315	0.315	tNET	RR	1	R20C61[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0/CLK
0.459	0.144	tC2Q	RR	1	R20C61[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0/Q
0.890	0.431	tNET	RR	1	R25C61[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.239	0.658	tNET	RR	1	R25C61[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0/CLK
1.274	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0
1.255	-0.019	tHld		1	R25C61[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0

Path Statistics:

Clock Skew	0.924
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.431, 74.957%; tC2Q: 0.144, 25.043%
Required Clock Path Delay	cell: 0.581, 46.890%; route: 0.658, 53.110%

Path20

Path Summary:

Slack	-0.357
Data Arrival Time	0.898
Data Required Time	1.255
From	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	camera_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.315	0.315	tNET	RR	1	R20C61[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0/CLK
0.459	0.144	tC2Q	RR	1	R20C61[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0/Q
0.898	0.439	tNET	RR	1	R25C61[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					camera_pclk
0.000	0.000	tCL	RR	1	IOR18[B]	camera_pclk_ibuf/I
0.581	0.581	tINS	RR	101	IOR18[B]	camera_pclk_ibuf/O
1.239	0.658	tNET	RR	1	R25C61[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0/CLK
1.274	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0
1.255	-0.019	tHld		1	R25C61[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0

Path Statistics:

Clock Skew	0.924
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.439, 75.300%; tC2Q: 0.144, 24.700%
Required Clock Path Delay	cell: 0.581, 46.890%; route: 0.658, 53.110%

Path21

Path Summary:

Slack	-0.256
Data Arrival Time	20.660
Data Required Time	20.915
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_1_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	clk50m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.299	0.299	tNET	RR	1	R35C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_1_s0/CLK
20.441	0.141	tC2Q	RF	1	R35C31[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_1_s0/Q
20.507	0.066	tNET	FF	1	R35C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_Z_s/I1
20.660	0.153	tINS	FF	1	R35C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_Z_s/F
20.660	0.000	tNET	FF	1	R35C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk50m
20.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
20.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
20.879	0.298	tNET	RR	1	R35C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLK
20.914	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0
20.915	0.001	tHld		1	R35C31[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0

Path Statistics:

Clock Skew	0.580
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%
Arrival Data Path Delay	cell: 0.153, 42.500%; route: 0.066, 18.333%; tC2Q: 0.141, 39.167%
Required Clock Path Delay	cell: 0.581, 66.058%; route: 0.298, 33.942%

Path22

Path Summary:

Slack	0.109
Data Arrival Time	0.619
Data Required Time	0.510
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.301	0.301	tNET	RR	1	R8C45[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/CLK
0.445	0.144	tC2Q	RR	1	R8C45[1][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q
0.619	0.174	tNET	RR	1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[22]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.295	0.295	tNET	RR	1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.510	0.215	tHld		1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Path23

Path Summary:

Slack	0.109
Data Arrival Time	0.619
Data Required Time	0.510
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.301	0.301	tNET	RR	1	R8C45[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0/CLK
0.445	0.144	tC2Q	RR	1	R8C45[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0/Q
0.619	0.174	tNET	RR	1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[21]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.295	0.295	tNET	RR	1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.510	0.215	tHld		1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Path24

Path Summary:

Slack	0.109
Data Arrival Time	0.619
Data Required Time	0.510
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.301	0.301	tNET	RR	1	R8C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK
0.445	0.144	tC2Q	RR	1	R8C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q
0.619	0.174	tNET	RR	1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.295	0.295	tNET	RR	1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.510	0.215	tHld		1	BSRAM_R10[13]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Path25

Path Summary:

Slack	0.126
Data Arrival Time	0.636
Data Required Time	0.510
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_99_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.316	0.316	tNET	RR	1	R24C51[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_99_s0/CLK
0.460	0.144	tC2Q	RR	1	R24C51[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_99_s0/Q
0.636	0.176	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.295	0.295	tNET	RR	1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.510	0.215	tHld		1	BSRAM_R28[15]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.316, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.167
Data Arrival Time	3.050
Data Required Time	1.883
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.883	-0.420	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	-1.167
Data Arrival Time	3.050
Data Required Time	1.883
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.883	-0.420	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
2.172	-0.130	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
2.172	-0.130	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
2.172	-0.130	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
2.172	-0.130	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
2.172	-0.130	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
2.172	-0.130	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	-0.878
Data Arrival Time	3.050
Data Required Time	2.172
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.250	1.250					active clock edge time
1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
2.337	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
2.337	0.000	tNET	FF	1	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/FCLK
2.302	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
2.172	-0.130	tSu		1	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	0.081
Data Arrival Time	3.050
Data Required Time	3.131
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.131	-0.422	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	0.081
Data Arrival Time	3.050
Data Required Time	3.131
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.131	-0.422	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	0.370
Data Arrival Time	3.050
Data Required Time	3.420
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
3.420	-0.132	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	0.370
Data Arrival Time	3.050
Data Required Time	3.420
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
3.420	-0.132	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	0.370
Data Arrival Time	3.050
Data Required Time	3.420
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
3.420	-0.132	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	0.370
Data Arrival Time	3.050
Data Required Time	3.420
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
3.420	-0.132	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	0.370
Data Arrival Time	3.050
Data Required Time	3.420
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
3.420	-0.132	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	0.370
Data Arrival Time	3.050
Data Required Time	3.420
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
3.587	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
3.587	0.000	tNET	RR	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
3.552	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
3.420	-0.132	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	-0.208
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	7.210
Data Arrival Time	3.050
Data Required Time	10.260
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
10.689	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
10.260	-0.429	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.571
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path19

Path Summary:

Slack	7.210
Data Arrival Time	3.050
Data Required Time	10.260
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
10.689	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
10.260	-0.429	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.571
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path20

Path Summary:

Slack	7.500
Data Arrival Time	3.050
Data Required Time	10.550
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.717	0.717	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK
10.682	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
10.550	-0.132	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	-0.579
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path21

Path Summary:

Slack	7.508
Data Arrival Time	3.050
Data Required Time	10.558
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/PCLK
10.689	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
10.558	-0.132	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	-0.571
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path22

Path Summary:

Slack	7.508
Data Arrival Time	3.050
Data Required Time	10.558
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK
10.689	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
10.558	-0.132	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	-0.571
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path23

Path Summary:

Slack	7.508
Data Arrival Time	3.050
Data Required Time	10.558
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK
10.689	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
10.558	-0.132	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	-0.571
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path24

Path Summary:

Slack	7.508
Data Arrival Time	3.050
Data Required Time	10.558
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.724	0.725	tNET	RR	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/PCLK
10.689	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
10.558	-0.132	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	-0.571
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path25

Path Summary:

Slack	7.515
Data Arrival Time	3.050
Data Required Time	10.565
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
1.296	0.709	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.590	0.294	tC2Q	RF	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.050	1.460	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.732	0.732	tNET	RR	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK
10.697	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
10.565	-0.132	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	-0.564
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 45.300%; route: 0.709, 54.700%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.460, 83.241%; tC2Q: 0.294, 16.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.732, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.153
Data Arrival Time	1.725
Data Required Time	1.571
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.405	0.317	tINS	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.405	0.000	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.440	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.571	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.516
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.317, 100.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	0.153
Data Arrival Time	1.725
Data Required Time	1.571
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.405	0.317	tINS	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.405	0.000	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.440	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.571	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.516
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.317, 100.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	0.230
Data Arrival Time	1.725
Data Required Time	1.495
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.328	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.328	0.000	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
1.363	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.495	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.439
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.240, 100.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	0.230
Data Arrival Time	1.725
Data Required Time	1.495
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.328	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.328	0.000	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
1.363	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.495	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.439
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.240, 100.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	0.230
Data Arrival Time	1.725
Data Required Time	1.495
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.328	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.328	0.000	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
1.363	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.495	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.439
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.240, 100.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	0.230
Data Arrival Time	1.725
Data Required Time	1.495
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.328	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.328	0.000	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
1.363	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.495	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.439
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.240, 100.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	0.230
Data Arrival Time	1.725
Data Required Time	1.495
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT76[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.328	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.328	0.000	tNET	RR	1	IOT76[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TCLK
1.363	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
1.495	0.132	tHld		1	IOT76[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem

Path Statistics:

Clock Skew	0.439
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.240, 100.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	0.470
Data Arrival Time	1.725
Data Required Time	1.254
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.122	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.254	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.198
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	0.470
Data Arrival Time	1.725
Data Required Time	1.254
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.122	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.254	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.198
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	0.470
Data Arrival Time	1.725
Data Required Time	1.254
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK
1.122	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.254	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.198
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	0.470
Data Arrival Time	1.725
Data Required Time	1.254
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK
1.122	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.254	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.198
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	0.470
Data Arrival Time	1.725
Data Required Time	1.254
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK
1.122	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.254	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.198
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	0.470
Data Arrival Time	1.725
Data Required Time	1.254
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
1.087	1.087	tCL	RR	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
1.087	0.000	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK
1.122	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.254	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.198
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	1.233
Data Arrival Time	1.725
Data Required Time	0.491
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.325	0.325	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.360	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
0.491	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	-0.564
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.325, 100.000%

Path15

Path Summary:

Slack	1.237
Data Arrival Time	1.725
Data Required Time	0.487
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.321	0.321	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.356	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.487	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.568
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path16

Path Summary:

Slack	1.237
Data Arrival Time	1.725
Data Required Time	0.487
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.321	0.321	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK
0.356	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
0.487	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	-0.568
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path17

Path Summary:

Slack	1.237
Data Arrival Time	1.725
Data Required Time	0.487
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.321	0.321	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/PCLK
0.356	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
0.487	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	-0.568
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path18

Path Summary:

Slack	1.241
Data Arrival Time	1.725
Data Required Time	0.483
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.317	0.317	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.352	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.483	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.572
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path19

Path Summary:

Slack	1.241
Data Arrival Time	1.725
Data Required Time	0.483
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000	0.000	tCL	RR	3936	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.317	0.317	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
0.352	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
0.483	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	-0.572
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path20

Path Summary:

Slack	1.387
Data Arrival Time	1.725
Data Required Time	0.338
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
-0.163	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
-0.163	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.173	0.335	tINS	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
0.173	0.000	tNET	FF	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
0.208	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.338	0.130	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.534
Hold Relationship	-1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.335, 100.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	1.387
Data Arrival Time	1.725
Data Required Time	0.338
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
-0.163	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
-0.163	0.000	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.173	0.335	tINS	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
0.173	0.000	tNET	FF	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
0.208	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.338	0.130	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.534
Hold Relationship	-1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.335, 100.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack	1.473
Data Arrival Time	1.725
Data Required Time	0.252
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
-0.163	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
-0.163	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.086	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
0.086	0.000	tNET	FF	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
0.121	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
0.252	0.130	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.448
Hold Relationship	-1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.249, 100.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	1.473
Data Arrival Time	1.725
Data Required Time	0.252
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
-0.163	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
-0.163	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.086	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
0.086	0.000	tNET	FF	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
0.121	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
0.252	0.130	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.448
Hold Relationship	-1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.249, 100.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	1.473
Data Arrival Time	1.725
Data Required Time	0.252
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
-0.163	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
-0.163	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.086	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
0.086	0.000	tNET	FF	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
0.121	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
0.252	0.130	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.448
Hold Relationship	-1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.249, 100.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	1.473
Data Arrival Time	1.725
Data Required Time	0.252
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	66	IOB29[A]	clk50m_ibuf/O
0.889	0.308	tNET	RR	1	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.033	0.144	tC2Q	RR	3133	R26C43[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
1.725	0.692	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-1.250	-1.250					active clock edge time
-1.250	0.000					ddr_pll/PLLA_inst/CLKOUT2.default_gen_clk
-0.163	1.087	tCL	FF	64	PLL_L[1]	ddr_pll/PLLA_inst/CLKOUT2
-0.163	0.000	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.086	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
0.086	0.000	tNET	FF	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
0.121	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
0.252	0.130	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.448
Hold Relationship	-1.250
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 65.352%; route: 0.308, 34.648%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.692, 82.770%; tC2Q: 0.144, 17.230%
Required Clock Path Delay	cell: 0.249, 100.000%; route: 0.000, 0.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.455
Actual Width:	4.317
Required Width:	0.862
Type:	High Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			camera_pclk
0.000	0.000	tCL	RR	camera_pclk_ibuf/I
0.587	0.587	tINS	RR	camera_pclk_ibuf/O
1.902	1.315	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.583	0.583	tINS	FF	camera_pclk_ibuf/O
6.218	0.636	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	3.455
Actual Width:	4.317
Required Width:	0.862
Type:	High Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			camera_pclk
0.000	0.000	tCL	RR	camera_pclk_ibuf/I
0.587	0.587	tINS	RR	camera_pclk_ibuf/O
1.902	1.315	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.583	0.583	tINS	FF	camera_pclk_ibuf/O
6.218	0.636	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

MPW3

MPW Summary:

Slack:	3.458
Actual Width:	4.320
Required Width:	0.862
Type:	High Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			camera_pclk
0.000	0.000	tCL	RR	camera_pclk_ibuf/I
0.587	0.587	tINS	RR	camera_pclk_ibuf/O
1.894	1.307	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.583	0.583	tINS	FF	camera_pclk_ibuf/O
6.214	0.632	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

MPW4

MPW Summary:

Slack:	3.458
Actual Width:	4.320
Required Width:	0.862
Type:	High Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			camera_pclk
0.000	0.000	tCL	RR	camera_pclk_ibuf/I
0.587	0.587	tINS	RR	camera_pclk_ibuf/O
1.894	1.307	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.583	0.583	tINS	FF	camera_pclk_ibuf/O
6.214	0.632	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

MPW5

MPW Summary:

Slack:	3.479
Actual Width:	4.341
Required Width:	0.862
Type:	Low Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.591	0.591	tINS	FF	camera_pclk_ibuf/O
6.883	1.292	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			camera_pclk
10.000	0.000	tCL	RR	camera_pclk_ibuf/I
10.581	0.581	tINS	RR	camera_pclk_ibuf/O
11.224	0.643	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

MPW6

MPW Summary:

Slack:	3.479
Actual Width:	4.341
Required Width:	0.862
Type:	Low Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.591	0.591	tINS	FF	camera_pclk_ibuf/O
6.883	1.292	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			camera_pclk
10.000	0.000	tCL	RR	camera_pclk_ibuf/I
10.581	0.581	tINS	RR	camera_pclk_ibuf/O
11.224	0.643	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

MPW7

MPW Summary:

Slack:	3.482
Actual Width:	4.344
Required Width:	0.862
Type:	Low Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.591	0.591	tINS	FF	camera_pclk_ibuf/O
6.875	1.284	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			camera_pclk
10.000	0.000	tCL	RR	camera_pclk_ibuf/I
10.581	0.581	tINS	RR	camera_pclk_ibuf/O
11.220	0.639	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

MPW8

MPW Summary:

Slack:	3.482
Actual Width:	4.344
Required Width:	0.862
Type:	Low Pulse Width
Clock:	camera_pclk
Objects:	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			camera_pclk
5.000	0.000	tCL	FF	camera_pclk_ibuf/I
5.591	0.591	tINS	FF	camera_pclk_ibuf/O
6.875	1.284	tNET	FF	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			camera_pclk
10.000	0.000	tCL	RR	camera_pclk_ibuf/I
10.581	0.581	tINS	RR	camera_pclk_ibuf/O
11.220	0.639	tNET	RR	ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

MPW9

MPW Summary:

Slack:	3.737
Actual Width:	4.599
Required Width:	0.862
Type:	Low Pulse Width
Clock:	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects:	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
5.000	0.000	tCL	FF	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.700	0.700	tNET	FF	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.299	0.299	tNET	RR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA

MPW10

MPW Summary:

Slack:	3.737
Actual Width:	4.599
Required Width:	0.862
Type:	Low Pulse Width
Clock:	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects:	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
5.000	0.000	tCL	FF	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.700	0.700	tNET	FF	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.000	0.000	tCL	RR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.299	0.299	tNET	RR	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3936	ui_clk	-2.766	0.732
3133	ui_clk_sync_rst	-1.167	1.723
197	eye_calib_start_rr	6.696	2.539
195	ddr_init_internal_rr	6.213	3.008
180	eye_calib_start_rr[0]	5.428	3.560
149	dqsts1	6.822	2.477
148	dqs_reg	7.069	2.113
129	phy_rddata_valid_d1	6.573	3.099
124	raddr[2]	3.473	1.567
102	loc_clk50m	14.855	0.732

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R10C38	72.22%
R10C33	66.67%
R10C39	65.28%
R10C36	59.72%
R10C62	59.72%
R28C59	58.33%
R10C63	58.33%
R10C41	58.33%
R10C45	58.33%
R26C60	56.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command