Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v H:\0_gaoyun_p\1.9.9.01\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Mon Nov 25 10:40:00 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.878s, Peak memory usage = 152.312MB Running netlist conversion: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 152.312MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 152.312MB Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 152.312MB Optimizing Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.403s, Peak memory usage = 152.312MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 152.312MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 152.312MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 152.312MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 152.312MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 152.312MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 152.312MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 152.312MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 166.527MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 166.527MB Generate output files: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.386s, Peak memory usage = 166.527MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 166.527MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 371 |
| I/O Buf | 365 |
| IBUF | 182 |
| OBUF | 162 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 3645 |
| DFFSE | 1 |
| DFFRE | 445 |
| DFFPE | 66 |
| DFFCE | 3133 |
| LUT | 2300 |
| LUT2 | 410 |
| LUT3 | 1068 |
| LUT4 | 822 |
| ALU | 166 |
| ALU | 166 |
| INV | 27 |
| INV | 27 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 12 |
| SDPB | 4 |
| SDPX9B | 8 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2493(2327 LUT, 166 ALU) / 23040 | 11% |
| Register | 3645 / 23685 | 16% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 3645 / 23685 | 16% |
| BSRAM | 12 / 56 | 22% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
| gw3_top/u_ddr_phy_top/u_ddr_init/n1981_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw3_top/u_ddr_phy_top/u_ddr_init/n1981_s2/O | ||
| gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.000(MHz) | 1394.294(MHz) | 1 | TOP |
| 2 | clk | 100.000(MHz) | 260.960(MHz) | 6 | TOP |
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 725.690(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.538 |
| Data Arrival Time | 1.881 |
| Data Required Time | 5.419 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.254 | 0.254 | tCL | RR | 3692 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.554 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 0.860 | 0.306 | tC2Q | RR | 12 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 1.160 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 1.581 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 1.881 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.591 | 0.591 | tINS | FF | 64 | memory_clk_ibuf/O |
| 5.871 | 0.280 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.836 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.419 | -0.417 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.317 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | 3.538 |
| Data Arrival Time | 1.881 |
| Data Required Time | 5.419 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.254 | 0.254 | tCL | RR | 3692 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.554 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 0.860 | 0.306 | tC2Q | RR | 12 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 1.160 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 1.581 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 1.881 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.591 | 0.591 | tINS | FF | 64 | memory_clk_ibuf/O |
| 5.871 | 0.280 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 5.836 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.419 | -0.417 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.317 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 0.421, 31.726%; route: 0.600, 45.214%; tC2Q: 0.306, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | 6.151 |
| Data Arrival Time | 34.317 |
| Data Required Time | 40.468 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.587 | 0.587 | tINS | RR | 39 | clk_ibuf/O |
| 30.887 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 31.193 | 0.306 | tC2Q | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 31.493 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s24/I0 |
| 31.914 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s24/F |
| 32.214 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/I1 |
| 32.627 | 0.413 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/F |
| 32.927 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/I2 |
| 33.296 | 0.369 | tINS | RR | 18 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/F |
| 33.596 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/I0 |
| 34.017 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/F |
| 34.317 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.254 | 0.254 | tCL | RR | 3692 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.554 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/CLK |
| 40.519 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 | ||
| 40.468 | -0.051 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 |
| Clock Skew: | -0.333 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
| Arrival Data Path Delay: | cell: 1.624, 47.347%; route: 1.500, 43.732%; tC2Q: 0.306, 8.921% |
| Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Path 4
Path Summary:| Slack | 6.151 |
| Data Arrival Time | 34.317 |
| Data Required Time | 40.468 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.587 | 0.587 | tINS | RR | 39 | clk_ibuf/O |
| 30.887 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 31.193 | 0.306 | tC2Q | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 31.493 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s24/I0 |
| 31.914 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s24/F |
| 32.214 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/I1 |
| 32.627 | 0.413 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/F |
| 32.927 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/I2 |
| 33.296 | 0.369 | tINS | RR | 18 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/F |
| 33.596 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/I0 |
| 34.017 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/F |
| 34.317 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.254 | 0.254 | tCL | RR | 3692 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.554 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/CLK |
| 40.519 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 | ||
| 40.468 | -0.051 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 |
| Clock Skew: | -0.333 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
| Arrival Data Path Delay: | cell: 1.624, 47.347%; route: 1.500, 43.732%; tC2Q: 0.306, 8.921% |
| Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Path 5
Path Summary:| Slack | 6.151 |
| Data Arrival Time | 34.317 |
| Data Required Time | 40.468 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.587 | 0.587 | tINS | RR | 39 | clk_ibuf/O |
| 30.887 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 31.193 | 0.306 | tC2Q | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 31.493 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s24/I0 |
| 31.914 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s24/F |
| 32.214 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/I1 |
| 32.627 | 0.413 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.EYE_SCAN_s22/F |
| 32.927 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/I2 |
| 33.296 | 0.369 | tINS | RR | 18 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/F |
| 33.596 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_WAIT_s19/I0 |
| 34.017 | 0.421 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_WAIT_s19/F |
| 34.317 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.254 | 0.254 | tCL | RR | 3692 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.554 | 0.300 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0/CLK |
| 40.519 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0 | ||
| 40.468 | -0.051 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_LOAD_MR1_WAIT_s0 |
| Clock Skew: | -0.333 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
| Arrival Data Path Delay: | cell: 1.624, 47.347%; route: 1.500, 43.732%; tC2Q: 0.306, 8.921% |
| Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |