# Reading D:/Quartus13.0/modelsim_ase/tcl/vsim/pref.tcl 
# do uart_loopback_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\Quartus13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\Quartus13.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+D:/li/AC606/uart_loopback {D:/li/AC606/uart_loopback/uart_loopback.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_loopback
# 
# Top level modules:
# 	uart_loopback
# vlog -vlog01compat -work work +incdir+D:/li/AC606/uart_loopback {D:/li/AC606/uart_loopback/uart_data_tx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_data_tx
# 
# Top level modules:
# 	uart_data_tx
# vlog -vlog01compat -work work +incdir+D:/li/AC606/uart_loopback {D:/li/AC606/uart_loopback/uart_data_rx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_data_rx
# 
# Top level modules:
# 	uart_data_rx
# vlog -vlog01compat -work work +incdir+D:/li/AC606/uart_loopback {D:/li/AC606/uart_loopback/uart_byte_tx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_tx
# 
# Top level modules:
# 	uart_byte_tx
# vlog -vlog01compat -work work +incdir+D:/li/AC606/uart_loopback {D:/li/AC606/uart_loopback/uart_byte_rx.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_byte_rx
# 
# Top level modules:
# 	uart_byte_rx
# 
# vlog -vlog01compat -work work +incdir+D:/li/AC606/uart_loopback {D:/li/AC606/uart_loopback/uart_loopback_tb.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module uart_loopback_tb
# 
# Top level modules:
# 	uart_loopback_tb
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  uart_loopback_tb
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps uart_loopback_tb 
# Loading work.uart_loopback_tb
# Loading work.uart_data_tx
# Loading work.uart_byte_tx
# Loading work.uart_loopback
# Loading work.uart_data_rx
# Loading work.uart_byte_rx
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Break in Module uart_loopback_tb at D:/li/AC606/uart_loopback/uart_loopback_tb.v line 86
# Simulation Breakpoint: Break in Module uart_loopback_tb at D:/li/AC606/uart_loopback/uart_loopback_tb.v line 86
# MACRO ./uart_loopback_run_msim_rtl_verilog.do PAUSED at line 21
