# PIN MAP for core < ddr3_qsys_mem_if_ddr3_emif_p0 >
#
# Generated by ddr3_qsys_mem_if_ddr3_emif_p0_pin_assignments.tcl
#
# This file is for reference only and is not used by Quartus Prime
#

INSTANCE: u0|mem_if_ddr3_emif
DQS: {DDR3_DQS_p[0]} {DDR3_DQS_p[1]} {DDR3_DQS_p[2]} {DDR3_DQS_p[3]}
DQSn: {DDR3_DQS_n[0]} {DDR3_DQS_n[1]} {DDR3_DQS_n[2]} {DDR3_DQS_n[3]}
DQ: {{DDR3_DQ[0]} {DDR3_DQ[1]} {DDR3_DQ[2]} {DDR3_DQ[3]} {DDR3_DQ[4]} {DDR3_DQ[5]} {DDR3_DQ[6]} {DDR3_DQ[7]}} {{DDR3_DQ[8]} {DDR3_DQ[9]} {DDR3_DQ[10]} {DDR3_DQ[11]} {DDR3_DQ[12]} {DDR3_DQ[13]} {DDR3_DQ[14]} {DDR3_DQ[15]}} {{DDR3_DQ[16]} {DDR3_DQ[17]} {DDR3_DQ[18]} {DDR3_DQ[19]} {DDR3_DQ[20]} {DDR3_DQ[21]} {DDR3_DQ[22]} {DDR3_DQ[23]}} {{DDR3_DQ[24]} {DDR3_DQ[25]} {DDR3_DQ[26]} {DDR3_DQ[27]} {DDR3_DQ[28]} {DDR3_DQ[29]} {DDR3_DQ[30]} {DDR3_DQ[31]}}
DM {DDR3_DM[0]} {DDR3_DM[1]} {DDR3_DM[2]} {DDR3_DM[3]}
CK: DDR3_CK_p
CKn: DDR3_CK_n
ADD: {DDR3_A[0]} {DDR3_A[10]} {DDR3_A[11]} {DDR3_A[12]} {DDR3_A[1]} {DDR3_A[2]} {DDR3_A[3]} {DDR3_A[4]} {DDR3_A[5]} {DDR3_A[6]} {DDR3_A[7]} {DDR3_A[8]} {DDR3_A[9]}
CMD: DDR3_CS_n DDR3_WE_n DDR3_RAS_n DDR3_CAS_n DDR3_ODT DDR3_CKE
RESET: DDR3_RESET_n
BA: {DDR3_BA[0]} {DDR3_BA[1]} {DDR3_BA[2]}
REF CLK: MAX10_CLK3_50
PLL AFI: u0|mem_if_ddr3_emif|pll0|pll1~PLL_OUTPUT_COUNTER|divclk
PLL AFI PHY: u0|mem_if_ddr3_emif|pll0|pll1_phy~PLL_OUTPUT_COUNTER|divclk
PLL CK: u0|mem_if_ddr3_emif|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk
PLL DQ WRITE: u0|mem_if_ddr3_emif|pll0|pll3~PLL_OUTPUT_COUNTER|divclk
PLL WRITE: u0|mem_if_ddr3_emif|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk
PLL AC: u0|mem_if_ddr3_emif|pll0|pll4~PLL_OUTPUT_COUNTER|divclk
PLL AVL: u0|mem_if_ddr3_emif|pll0|pll6~PLL_OUTPUT_COUNTER|divclk
PLL CONFIG: u0|mem_if_ddr3_emif|pll0|pll7~PLL_OUTPUT_COUNTER|divclk
DQS_IN_CLOCK DQS_PIN (0): DDR3_DQS_p[0]
DQS_IN_CLOCK DQS_SHIFTED_PIN (0): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (0): u0|mem_if_ddr3_emif|div_clock_0
DQS_IN_CLOCK DIV_PIN (0): u0|mem_if_ddr3_emif|p0|umemphy|uread_datapath|read_capture_clk_div2[0]
DQS_IN_CLOCK DQS_PIN (1): DDR3_DQS_p[1]
DQS_IN_CLOCK DQS_SHIFTED_PIN (1): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (1): u0|mem_if_ddr3_emif|div_clock_1
DQS_IN_CLOCK DIV_PIN (1): u0|mem_if_ddr3_emif|p0|umemphy|uread_datapath|read_capture_clk_div2[1]
DQS_IN_CLOCK DQS_PIN (2): DDR3_DQS_p[2]
DQS_IN_CLOCK DQS_SHIFTED_PIN (2): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (2): u0|mem_if_ddr3_emif|div_clock_2
DQS_IN_CLOCK DIV_PIN (2): u0|mem_if_ddr3_emif|p0|umemphy|uread_datapath|read_capture_clk_div2[2]
DQS_IN_CLOCK DQS_PIN (3): DDR3_DQS_p[3]
DQS_IN_CLOCK DQS_SHIFTED_PIN (3): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (3): u0|mem_if_ddr3_emif|div_clock_3
DQS_IN_CLOCK DIV_PIN (3): u0|mem_if_ddr3_emif|p0|umemphy|uread_datapath|read_capture_clk_div2[3]
DQS_OUT_CLOCK SRC (0): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (0): DDR3_DQS_p[0]
DQS_OUT_CLOCK DM (0): DDR3_DM[0]
DQS_OUT_CLOCK SRC (1): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (1): DDR3_DQS_p[1]
DQS_OUT_CLOCK DM (1): DDR3_DM[1]
DQS_OUT_CLOCK SRC (2): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (2): DDR3_DQS_p[2]
DQS_OUT_CLOCK DM (2): DDR3_DM[2]
DQS_OUT_CLOCK SRC (3): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (3): DDR3_DQS_p[3]
DQS_OUT_CLOCK DM (3): DDR3_DM[3]
DQSN_OUT_CLOCK SRC (0): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (0): DDR3_DQS_n[0]
DQSN_OUT_CLOCK DM (0): DDR3_DM[0]
DQSN_OUT_CLOCK SRC (1): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (1): DDR3_DQS_n[1]
DQSN_OUT_CLOCK DM (1): DDR3_DM[1]
DQSN_OUT_CLOCK SRC (2): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (2): DDR3_DQS_n[2]
DQSN_OUT_CLOCK DM (2): DDR3_DM[2]
DQSN_OUT_CLOCK SRC (3): u0|mem_if_ddr3_emif|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (3): DDR3_DQS_n[3]
DQSN_OUT_CLOCK DM (3): DDR3_DM[3]
READ CAPTURE DDIO: {*:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}
AFI RESET REGISTERS: *:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3]
SEQ  RESET REGISTERS: *:u0|*:mem_if_ddr3_emif|*:s0|*
SYNCHRONIZERS: *:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync
SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
SYNCHRONIZATION FIFO WRITE REGISTERS: *:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF*
SYNCHRONIZATION FIFO READ REGISTERS: *:u0|*:mem_if_ddr3_emif|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*]

#
# END OF INSTANCE: u0|mem_if_ddr3_emif

