name: ddr3_qsys_mem_if_ddr3_emif_s0
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/ddr3_qsys_mem_if_ddr3_emif_s0.v (26183)
generated files (children of this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_mem_if_sequencer_rst.sv (3274)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/sequencer_m10.sv (55126)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/sequencer_pll_mgr.sv (5724)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/sequencer_phy_mgr.sv (18655)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ddr3.v (7993)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ac_ROM_reg.v (1407)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_bitcheck.v (3299)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_core.sv (20315)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_data_broadcast.v (2289)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_data_decoder.v (2809)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_datamux.v (1691)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_di_buffer.v (3934)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_di_buffer_wrap.v (2631)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_dm_decoder.v (1685)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_generic.sv (18402)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_inst_ROM_reg.v (1430)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_jumplogic.v (3643)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_lfsr72.v (1337)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_lfsr36.v (2025)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_lfsr12.v (1390)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_pattern_fifo.v (2756)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ram.v (1263)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ram_csr.v (2433)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_read_datapath.v (4000)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_write_decoder.v (2746)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0.v (118290)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_master_translator.sv (20557)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_slave_translator.sv (17338)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_master_agent.sv (11333)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_slave_agent.sv (29997)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_burst_uncompressor.sv (13717)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_avalon_sc_fifo.v (34467)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router.sv (8482)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001.sv (7585)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux.sv (4810)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv (9530)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux.sv (3843)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux.sv (3581)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv (9530)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux.sv (12924)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter.v (6240)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv (3812)
Instantiates the following:
   sequencer_rst : altera_mem_if_sequencer_rst
   cpu_inst : sequencer_m10
   sequencer_pll_mgr_inst : sequencer_pll_mgr
   sequencer_phy_mgr_inst : sequencer_phy_mgr
   sequencer_rw_mgr_inst : rw_manager_ddr3
   mm_interconnect_0 : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0
 
name: altera_mem_if_sequencer_rst
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_mem_if_sequencer_rst.sv (3274)
 
name: sequencer_m10
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/sequencer_m10.sv (55126)
 
name: sequencer_pll_mgr
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/sequencer_pll_mgr.sv (5724)
 
name: sequencer_phy_mgr
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/sequencer_phy_mgr.sv (18655)
 
name: rw_manager_ddr3
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ddr3.v (7993)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ac_ROM_reg.v (1407)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_bitcheck.v (3299)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_core.sv (20315)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_data_broadcast.v (2289)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_data_decoder.v (2809)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_datamux.v (1691)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_di_buffer.v (3934)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_di_buffer_wrap.v (2631)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_dm_decoder.v (1685)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_generic.sv (18402)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_inst_ROM_reg.v (1430)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_jumplogic.v (3643)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_lfsr72.v (1337)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_lfsr36.v (2025)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_lfsr12.v (1390)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_pattern_fifo.v (2756)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ram.v (1263)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_ram_csr.v (2433)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_read_datapath.v (4000)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/rw_manager_write_decoder.v (2746)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0.v (118290)
generated files (children of this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_master_translator.sv (20557)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_slave_translator.sv (17338)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_master_agent.sv (11333)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_slave_agent.sv (29997)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_burst_uncompressor.sv (13717)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_avalon_sc_fifo.v (34467)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router.sv (8482)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001.sv (7585)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux.sv (4810)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv (9530)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux.sv (3843)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux.sv (3581)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv (9530)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux.sv (12924)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter.v (6240)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv (3812)
Instantiates the following:
   cpu_inst_data_master_translator : altera_merlin_master_translator
   sequencer_phy_mgr_inst_avl_translator, sequencer_rw_mgr_inst_avl_translator, sequencer_pll_mgr_inst_avl_translator : altera_merlin_slave_translator
   cpu_inst_data_master_agent : altera_merlin_master_agent
   sequencer_phy_mgr_inst_avl_agent, sequencer_rw_mgr_inst_avl_agent, sequencer_pll_mgr_inst_avl_agent : altera_merlin_slave_agent
   sequencer_phy_mgr_inst_avl_agent_rsp_fifo, sequencer_rw_mgr_inst_avl_agent_rsp_fifo, sequencer_pll_mgr_inst_avl_agent_rsp_fifo : altera_avalon_sc_fifo
   router : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router
   router_001, router_002, router_003 : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001
   cmd_demux : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux
   cmd_mux, cmd_mux_001, cmd_mux_002 : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux
   rsp_demux, rsp_demux_001, rsp_demux_002 : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux
   rsp_mux : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux
   avalon_st_adapter, avalon_st_adapter_001, avalon_st_adapter_002 : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter
 
name: altera_merlin_master_translator
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_master_translator.sv (20557)
 
name: altera_merlin_slave_translator
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_slave_translator.sv (17338)
 
name: altera_merlin_master_agent
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_master_agent.sv (11333)
 
name: altera_merlin_slave_agent
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_slave_agent.sv (29997)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_burst_uncompressor.sv (13717)
 
name: altera_avalon_sc_fifo
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_avalon_sc_fifo.v (34467)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router.sv (8482)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001.sv (7585)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux.sv (4810)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv (9530)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux.sv (3843)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux.sv (3581)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv (9530)
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux.sv (12924)
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter.v (6240)
generated files (children of this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv (3812)
Instantiates the following:
   error_adapter_0 : ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0
 
name: ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0
generated files (just this core):
   F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv (3812)
 
 
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.avl_clk: Timing: ELA:1/0.000s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.sequencer_rst: Timing: VAL:1/0.000s ELA:1/0.020s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.cpu_inst: Timing: VAL:2/0.000s/0.000s ELA:2/0.012s/0.022s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.sequencer_pll_mgr_inst: Timing: VAL:1/0.000s ELA:1/0.763s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.sequencer_phy_mgr_inst: Timing: VAL:1/0.000s ELA:1/0.021s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.afi_clk: Timing: ELA:1/0.000s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.afi_reset: Timing: ELA:1/0.002s
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0.sequencer_rw_mgr_inst: Timing: VAL:1/0.003s ELA:1/0.017s
 [Warning] ddr3_qsys_mem_if_ddr3_emif_s0.sequencer_rst: <b>sequencer_rst.clken_out</b> must be exported, or connected to a matching conduit.
 [Warning] ddr3_qsys_mem_if_ddr3_emif_s0.sequencer_rw_mgr_inst: <b>sequencer_rw_mgr_inst.csr</b> must be exported, or connected to a matching conduit.
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: Timing: VAL:1/0.000s COM:1/3.095s
 [Info] ddr3_qsys_mem_if_ddr3_emif_s0: Generating <b>qsys_sequencer_110</b> "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" for QUARTUS_SYNTH
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 0 starting:qsys_sequencer_110 "ddr3_qsys_mem_if_ddr3_emif_s0"
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] Transform: CustomInstructionTransform
 [Debug] No custom instruction connections, skipping transform 
 [Debug] merlin_custom_instruction_transform: After transform: <b>8</b> modules, <b>14</b> connections
 [Debug] Transform: MMTransform
 [Debug] Transform: InitialInterconnectTransform
 [Debug] merlin_initial_interconnect_transform: After transform: <b>6</b> modules, <b>11</b> connections
 [Debug] Transform: TerminalIdAssignmentUpdateTransform
 [Debug] Transform: DefaultSlaveTransform
 [Debug] Transform: TranslatorTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] merlin_translator_transform: After transform: <b>10</b> modules, <b>23</b> connections
 [Debug] Transform: IDPadTransform
 [Debug] Transform: DomainTransform
 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_inst.data_master and cpu_inst_data_master_translator.avalon_anti_master_0
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_phy_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_phy_mgr_inst.avl
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_rw_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_rw_mgr_inst.avl
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_pll_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_pll_mgr_inst.avl
 [Debug] merlin_domain_transform: After transform: <b>18</b> modules, <b>63</b> connections
 [Debug] Transform: RouterTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] merlin_router_transform: After transform: <b>22</b> modules, <b>75</b> connections
 [Debug] Transform: TrafficLimiterTransform
 [Debug] Transform: BurstTransform
 [Debug] Transform: TreeTransform
 [Debug] Transform: NetworkToSwitchTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] merlin_network_to_switch_transform: After transform: <b>29</b> modules, <b>89</b> connections
 [Debug] Transform: WidthTransform
 [Debug] Transform: RouterTableTransform
 [Debug] Transform: ThreadIDMappingTableTransform
 [Debug] Transform: ClockCrossingTransform
 [Debug] Transform: PipelineTransform
 [Debug] Transform: SpotPipelineTransform
 [Debug] Transform: PerformanceMonitorTransform
 [Debug] Transform: TrafficLimiterUpdateTransform
 [Debug] Transform: InsertClockAndResetBridgesTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] merlin_clock_and_reset_bridge_transform: After transform: <b>32</b> modules, <b>119</b> connections
 [Debug] Transform: InterconnectConnectionsTagger
 [Debug] Transform: HierarchyTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] merlin_hierarchy_transform: After transform: <b>9</b> modules, <b>18</b> connections
 [Debug] merlin_mm_transform: After transform: <b>9</b> modules, <b>18</b> connections
 [Debug] Transform: InterruptMapperTransform
 [Debug] Transform: InterruptSyncTransform
 [Debug] Transform: InterruptFanoutTransform
 [Debug] Transform: AvalonStreamingTransform
 [Debug] Transform: ResetAdaptation
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" reuses <b>altera_mem_if_sequencer_rst</b> "<b>submodules/altera_mem_if_sequencer_rst</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" reuses <b>sequencer_m10</b> "<b>submodules/sequencer_m10</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" reuses <b>sequencer_pll_mgr_140</b> "<b>submodules/sequencer_pll_mgr</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" reuses <b>sequencer_phy_mgr_100</b> "<b>submodules/sequencer_phy_mgr</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" reuses <b>sequencer_rw_mgr_ddr3_110</b> "<b>submodules/rw_manager_ddr3</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 5 starting:altera_mem_if_sequencer_rst "submodules/altera_mem_if_sequencer_rst"
 [Info] sequencer_rst: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" instantiated <b>altera_mem_if_sequencer_rst</b> "<b>sequencer_rst</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 4 starting:sequencer_m10 "submodules/sequencer_m10"
 [Info] cpu_inst: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" instantiated <b>sequencer_m10</b> "<b>cpu_inst</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 3 starting:sequencer_pll_mgr_140 "submodules/sequencer_pll_mgr"
 [Info] sequencer_pll_mgr_inst: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" instantiated <b>sequencer_pll_mgr_140</b> "<b>sequencer_pll_mgr_inst</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 2 starting:sequencer_phy_mgr_100 "submodules/sequencer_phy_mgr"
 [Info] sequencer_phy_mgr_inst: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" instantiated <b>sequencer_phy_mgr_100</b> "<b>sequencer_phy_mgr_inst</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 1 starting:sequencer_rw_mgr_ddr3_110 "submodules/rw_manager_ddr3"
 [Info] sequencer_rw_mgr_inst: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" instantiated <b>sequencer_rw_mgr_ddr3_110</b> "<b>sequencer_rw_mgr_inst</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 0 starting:altera_mm_interconnect "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0"
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] Transform: CustomInstructionTransform
 [Debug] No custom instruction connections, skipping transform 
 [Debug] merlin_custom_instruction_transform: After transform: <b>26</b> modules, <b>79</b> connections
 [Debug] Transform: MMTransform
 [Debug] Transform: InitialInterconnectTransform
 [Debug] merlin_initial_interconnect_transform: After transform: <b>0</b> modules, <b>0</b> connections
 [Debug] Transform: TerminalIdAssignmentUpdateTransform
 [Debug] Transform: DefaultSlaveTransform
 [Debug] Transform: TranslatorTransform
 [Debug] No Avalon connections, skipping transform 
 [Debug] Transform: IDPadTransform
 [Debug] Transform: DomainTransform
 [Debug] Transform: RouterTransform
 [Debug] Transform: TrafficLimiterTransform
 [Debug] Transform: BurstTransform
 [Debug] Transform: TreeTransform
 [Debug] Transform: NetworkToSwitchTransform
 [Debug] Transform: WidthTransform
 [Debug] Transform: RouterTableTransform
 [Debug] Transform: ThreadIDMappingTableTransform
 [Debug] Transform: ClockCrossingTransform
 [Debug] Transform: PipelineTransform
 [Debug] Transform: SpotPipelineTransform
 [Debug] Transform: PerformanceMonitorTransform
 [Debug] Transform: TrafficLimiterUpdateTransform
 [Debug] Transform: InsertClockAndResetBridgesTransform
 [Debug] Transform: InterconnectConnectionsTagger
 [Debug] Transform: HierarchyTransform
 [Debug] merlin_hierarchy_transform: After transform: <b>26</b> modules, <b>79</b> connections
 [Debug] Transform: InitialInterconnectTransform
 [Debug] merlin_initial_interconnect_transform: After transform: <b>0</b> modules, <b>0</b> connections
 [Debug] Transform: TerminalIdAssignmentUpdateTransform
 [Debug] Transform: DefaultSlaveTransform
 [Debug] Transform: TranslatorTransform
 [Debug] No Avalon connections, skipping transform 
 [Debug] Transform: IDPadTransform
 [Debug] Transform: DomainTransform
 [Debug] Transform: RouterTransform
 [Debug] Transform: TrafficLimiterTransform
 [Debug] Transform: BurstTransform
 [Debug] Transform: TreeTransform
 [Debug] Transform: NetworkToSwitchTransform
 [Debug] Transform: WidthTransform
 [Debug] Transform: RouterTableTransform
 [Debug] Transform: ThreadIDMappingTableTransform
 [Debug] Transform: ClockCrossingTransform
 [Debug] Transform: PipelineTransform
 [Debug] Transform: SpotPipelineTransform
 [Debug] Transform: PerformanceMonitorTransform
 [Debug] Transform: TrafficLimiterUpdateTransform
 [Debug] Transform: InsertClockAndResetBridgesTransform
 [Debug] Transform: InterconnectConnectionsTagger
 [Debug] Transform: HierarchyTransform
 [Debug] merlin_hierarchy_transform: After transform: <b>26</b> modules, <b>79</b> connections
 [Debug] Transform: InitialInterconnectTransform
 [Debug] merlin_initial_interconnect_transform: After transform: <b>0</b> modules, <b>0</b> connections
 [Debug] Transform: TerminalIdAssignmentUpdateTransform
 [Debug] Transform: DefaultSlaveTransform
 [Debug] Transform: TranslatorTransform
 [Debug] No Avalon connections, skipping transform 
 [Debug] Transform: IDPadTransform
 [Debug] Transform: DomainTransform
 [Debug] Transform: RouterTransform
 [Debug] Transform: TrafficLimiterTransform
 [Debug] Transform: BurstTransform
 [Debug] Transform: TreeTransform
 [Debug] Transform: NetworkToSwitchTransform
 [Debug] Transform: WidthTransform
 [Debug] Transform: RouterTableTransform
 [Debug] Transform: ThreadIDMappingTableTransform
 [Debug] Transform: ClockCrossingTransform
 [Debug] Transform: PipelineTransform
 [Debug] Transform: SpotPipelineTransform
 [Debug] Transform: PerformanceMonitorTransform
 [Debug] Transform: TrafficLimiterUpdateTransform
 [Debug] Transform: InsertClockAndResetBridgesTransform
 [Debug] Transform: InterconnectConnectionsTagger
 [Debug] Transform: HierarchyTransform
 [Debug] merlin_hierarchy_transform: After transform: <b>26</b> modules, <b>79</b> connections
 [Debug] Transform: InitialInterconnectTransform
 [Debug] merlin_initial_interconnect_transform: After transform: <b>0</b> modules, <b>0</b> connections
 [Debug] Transform: TerminalIdAssignmentUpdateTransform
 [Debug] Transform: DefaultSlaveTransform
 [Debug] Transform: TranslatorTransform
 [Debug] No Avalon connections, skipping transform 
 [Debug] Transform: IDPadTransform
 [Debug] Transform: DomainTransform
 [Debug] Transform: RouterTransform
 [Debug] Transform: TrafficLimiterTransform
 [Debug] Transform: BurstTransform
 [Debug] Transform: TreeTransform
 [Debug] Transform: NetworkToSwitchTransform
 [Debug] Transform: WidthTransform
 [Debug] Transform: RouterTableTransform
 [Debug] Transform: ThreadIDMappingTableTransform
 [Debug] Transform: ClockCrossingTransform
 [Debug] Transform: PipelineTransform
 [Debug] Transform: SpotPipelineTransform
 [Debug] Transform: PerformanceMonitorTransform
 [Debug] Transform: TrafficLimiterUpdateTransform
 [Debug] Transform: InsertClockAndResetBridgesTransform
 [Debug] Transform: InterconnectConnectionsTagger
 [Debug] Transform: HierarchyTransform
 [Debug] merlin_hierarchy_transform: After transform: <b>26</b> modules, <b>79</b> connections
 [Debug] Transform: InterruptMapperTransform
 [Debug] Transform: InterruptSyncTransform
 [Debug] Transform: InterruptFanoutTransform
 [Debug] Transform: AvalonStreamingTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] avalon_st_adapter: Inserting error_adapter: error_adapter_0
 [Debug] avalon_st_adapter.clk_bridge_0: Timing: ELA:1/0.000s
 [Debug] avalon_st_adapter.rst_bridge_0: Timing: ELA:2/0.001s/0.001s
 [Debug] avalon_st_adapter.error_adapter_0: Timing: ELA:1/0.019s
 [Debug] avalon_st_adapter: Timing: COM:3/0.049s/0.065s
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
 [Debug] avalon_st_adapter_001.clk_bridge_0: Timing: ELA:1/0.001s
 [Debug] avalon_st_adapter_001.rst_bridge_0: Timing: ELA:2/0.001s/0.002s
 [Debug] avalon_st_adapter_001.error_adapter_0: Timing: ELA:1/0.006s
 [Debug] avalon_st_adapter_001: Timing: COM:3/0.021s/0.022s
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
 [Debug] avalon_st_adapter_002.clk_bridge_0: Timing: ELA:1/0.000s
 [Debug] avalon_st_adapter_002.rst_bridge_0: Timing: ELA:2/0.001s/0.002s
 [Debug] avalon_st_adapter_002.error_adapter_0: Timing: ELA:1/0.008s
 [Debug] avalon_st_adapter_002: Timing: COM:3/0.036s/0.045s
 [Debug] com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform: After transform: <b>29</b> modules, <b>88</b> connections
 [Debug] Transform: ResetAdaptation
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter</b>"
 [Debug] mm_interconnect_0: "<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter</b>"
 [Info] mm_interconnect_0: "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 25 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"
 [Info] cpu_inst_data_master_translator: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>cpu_inst_data_master_translator</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 24 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"
 [Info] sequencer_phy_mgr_inst_avl_translator: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>sequencer_phy_mgr_inst_avl_translator</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 21 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"
 [Info] cpu_inst_data_master_agent: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_inst_data_master_agent</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 20 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"
 [Info] sequencer_phy_mgr_inst_avl_agent: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>sequencer_phy_mgr_inst_avl_agent</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 19 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"
 [Info] sequencer_phy_mgr_inst_avl_agent_rsp_fifo: "<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>sequencer_phy_mgr_inst_avl_agent_rsp_fifo</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 14 starting:altera_merlin_router "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router"
 [Info] router: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 13 starting:altera_merlin_router "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_router_001"
 [Info] router_001: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 10 starting:altera_merlin_demultiplexer "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_demux"
 [Info] cmd_demux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 9 starting:altera_merlin_multiplexer "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_cmd_mux"
 [Info] cmd_mux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 6 starting:altera_merlin_demultiplexer "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_demux"
 [Info] rsp_demux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 3 starting:altera_merlin_multiplexer "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_rsp_mux"
 [Info] rsp_mux: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"
 [Info] Reusing file <b>F:/SVN/neek10/test/yang/demo/ddr3_nios/ddr3_qsys_mem_if_ddr3_emif_s0/submodules/altera_merlin_arbitrator.sv</b>
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 2 starting:altera_avalon_st_adapter "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter"
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] Transform: CustomInstructionTransform
 [Debug] No custom instruction connections, skipping transform 
 [Debug] merlin_custom_instruction_transform: After transform: <b>3</b> modules, <b>3</b> connections
 [Debug] Transform: MMTransform
 [Debug] Transform: InterruptMapperTransform
 [Debug] Transform: InterruptSyncTransform
 [Debug] Transform: InterruptFanoutTransform
 [Debug] Transform: AvalonStreamingTransform
 [Debug] Transform: ResetAdaptation
 [Debug] avalon_st_adapter: "<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"
 [Info] avalon_st_adapter: "<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"
 [Debug] ddr3_qsys_mem_if_ddr3_emif_s0: queue size: 0 starting:error_adapter "submodules/ddr3_qsys_mem_if_ddr3_emif_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0"
 [Info] error_adapter_0: "<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"
 [Info] ddr3_qsys_mem_if_ddr3_emif_s0: Done "<b>ddr3_qsys_mem_if_ddr3_emif_s0</b>" with 20 modules, 42 files
