Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ad7606_ddr3_rgmii.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ad7606_driver.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\cmd_rx.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ddr3_memory_interface\ddr3_memory_interface.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ddr_pll\ddr_pll.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_cmd.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_pll\eth_pll.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_send_ctrl.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_udp_gmii\crc32_d8.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_udp_gmii\eth_udp_rx_gmii.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_udp_gmii\eth_udp_tx_gmii.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\eth_udp_gmii\ip_checksum.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\fifo_rx\fifo_rx.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\fifo_tx\fifo_tx.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\gmii_rgmii_gmii\gmii_to_rgmii.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\gmii_rgmii_gmii\rgmii_to_gmii.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\gowin_ddr\gowin_ddr.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\gowin_pll\gowin_pll.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\pll_100M\pll_100M.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\rd_data_fifo\rd_data_fifo.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\state_ctrl.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\wr_data_fifo\wr_data_fifo.v H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v H:\0_gaoyun_p\1.9.9\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\gw_jtag.v H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9 |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Thu Feb 6 13:41:25 2025 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | ad7606_ddr3_rgmii |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 979.027MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 979.027MB Optimizing Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.222s, Peak memory usage = 979.027MB Optimizing Phase 2: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.627s, Peak memory usage = 979.027MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 979.027MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 979.027MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 979.027MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 979.027MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.6s, Peak memory usage = 979.027MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.159s, Peak memory usage = 979.027MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 979.027MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 979.027MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.293s, Peak memory usage = 979.027MB Generate output files: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.454s, Peak memory usage = 979.027MB |
| Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 979.027MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 96 |
| I/O Buf | 93 |
| IBUF | 28 |
| OBUF | 44 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 5175 |
| DFFSE | 1 |
| DFFRE | 766 |
| DFFPE | 163 |
| DFFCE | 4245 |
| LUT | 4916 |
| LUT2 | 678 |
| LUT3 | 1907 |
| LUT4 | 2331 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 540 |
| ALU | 540 |
| SSRAM | 12 |
| RAM16S4 | 12 |
| INV | 55 |
| INV | 55 |
| IOLOGIC | 87 |
| IDDR | 5 |
| ODDR | 6 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 54 |
| SDPB | 46 |
| SDPX9B | 8 |
| CLOCK | 8 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| DHCE | 1 |
| PLLA | 3 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5591(4979 LUT, 540 ALU, 12 RAM16) / 23040 | 25% |
| Register | 5175 / 23685 | 22% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 5175 / 23685 | 22% |
| BSRAM | 54 / 56 | 97% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk50m | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | ||
| rgmii_rx_clk_i | Base | 8.000 | 125.0 | 0.000 | 4.000 | rgmii_rx_clk_i_ibuf/I | ||
| fifo_rx/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_rx/fifo_inst/n4_s2/O | ||
| fifo_rx/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_rx/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_s2/O | ||
| ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_s2/O | ||
| ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_s2/O | ||
| fifo_tx/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_tx/fifo_inst/n4_s2/O | ||
| fifo_tx/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_tx/fifo_inst/n9_s2/O | ||
| gw_gao_inst_0/u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n19_s2/O | ||
| Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 5.000 | 200.0 | 0.000 | 2.500 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT1 |
| pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | clk50m_ibuf/I | clk50m | pll_100M/PLLA_inst/CLKOUT0 |
| eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 8.000 | 125.0 | 0.000 | 4.000 | rgmii_rx_clk_i_ibuf/I | rgmii_rx_clk_i | eth_pll/PLLA_inst/CLKOUT0 |
| ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | Gowin_PLL/PLLA_inst/CLKOUT1 | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk50m | 50.0(MHz) | 304.3(MHz) | 6 | TOP |
| 2 | fifo_rx/fifo_inst/n4_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 3 | fifo_rx/fifo_inst/n9_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 4 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 5 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 6 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 7 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 8 | fifo_tx/fifo_inst/n4_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 9 | fifo_tx/fifo_inst/n9_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 10 | gw_gao_inst_0/u_icon_top/n19_6 | 100.0(MHz) | 1972.4(MHz) | 1 | TOP |
| 11 | Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | 200.0(MHz) | 1762.0(MHz) | 1 | TOP |
| 12 | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | 100.0(MHz) | 198.6(MHz) | 9 | TOP |
| 13 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | 125.0(MHz) | 192.7(MHz) | 11 | TOP |
| 14 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 178.0(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.458 |
| Data Arrival Time | 31.312 |
| Data Required Time | 32.770 |
| From | cmd_rx_0/RestartReq_s1 |
| To | RestartReq_0_d0_s0 |
| Launch Clk | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 30.706 | 0.706 | tCL | RR | 876 | pll_100M/PLLA_inst/CLKOUT0 |
| 30.856 | 0.150 | tNET | RR | 1 | cmd_rx_0/RestartReq_s1/CLK |
| 31.162 | 0.306 | tC2Q | RR | 4 | cmd_rx_0/RestartReq_s1/Q |
| 31.312 | 0.150 | tNET | RR | 1 | RestartReq_0_d0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 32.706 | 0.706 | tCL | RR | 749 | eth_pll/PLLA_inst/CLKOUT0 |
| 32.856 | 0.150 | tNET | RR | 1 | RestartReq_0_d0_s0/CLK |
| 32.821 | -0.035 | tUnc | RestartReq_0_d0_s0 | ||
| 32.770 | -0.051 | tSu | 1 | RestartReq_0_d0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.150, 32.895%; tC2Q: 0.306, 67.105% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
Path 2
Path Summary:| Slack | 1.458 |
| Data Arrival Time | 31.312 |
| Data Required Time | 32.770 |
| From | cmd_rx_0/DataNum_0_s0 |
| To | Number_d0_0_s0 |
| Launch Clk | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 30.706 | 0.706 | tCL | RR | 876 | pll_100M/PLLA_inst/CLKOUT0 |
| 30.856 | 0.150 | tNET | RR | 1 | cmd_rx_0/DataNum_0_s0/CLK |
| 31.162 | 0.306 | tC2Q | RR | 7 | cmd_rx_0/DataNum_0_s0/Q |
| 31.312 | 0.150 | tNET | RR | 1 | Number_d0_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 32.706 | 0.706 | tCL | RR | 749 | eth_pll/PLLA_inst/CLKOUT0 |
| 32.856 | 0.150 | tNET | RR | 1 | Number_d0_0_s0/CLK |
| 32.821 | -0.035 | tUnc | Number_d0_0_s0 | ||
| 32.770 | -0.051 | tSu | 1 | Number_d0_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.150, 32.895%; tC2Q: 0.306, 67.105% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
Path 3
Path Summary:| Slack | 1.458 |
| Data Arrival Time | 31.312 |
| Data Required Time | 32.770 |
| From | cmd_rx_0/DataNum_1_s0 |
| To | Number_d0_1_s0 |
| Launch Clk | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 30.706 | 0.706 | tCL | RR | 876 | pll_100M/PLLA_inst/CLKOUT0 |
| 30.856 | 0.150 | tNET | RR | 1 | cmd_rx_0/DataNum_1_s0/CLK |
| 31.162 | 0.306 | tC2Q | RR | 7 | cmd_rx_0/DataNum_1_s0/Q |
| 31.312 | 0.150 | tNET | RR | 1 | Number_d0_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 32.706 | 0.706 | tCL | RR | 749 | eth_pll/PLLA_inst/CLKOUT0 |
| 32.856 | 0.150 | tNET | RR | 1 | Number_d0_1_s0/CLK |
| 32.821 | -0.035 | tUnc | Number_d0_1_s0 | ||
| 32.770 | -0.051 | tSu | 1 | Number_d0_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.150, 32.895%; tC2Q: 0.306, 67.105% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
Path 4
Path Summary:| Slack | 1.458 |
| Data Arrival Time | 31.312 |
| Data Required Time | 32.770 |
| From | cmd_rx_0/DataNum_2_s0 |
| To | Number_d0_2_s0 |
| Launch Clk | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 30.706 | 0.706 | tCL | RR | 876 | pll_100M/PLLA_inst/CLKOUT0 |
| 30.856 | 0.150 | tNET | RR | 1 | cmd_rx_0/DataNum_2_s0/CLK |
| 31.162 | 0.306 | tC2Q | RR | 6 | cmd_rx_0/DataNum_2_s0/Q |
| 31.312 | 0.150 | tNET | RR | 1 | Number_d0_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 32.706 | 0.706 | tCL | RR | 749 | eth_pll/PLLA_inst/CLKOUT0 |
| 32.856 | 0.150 | tNET | RR | 1 | Number_d0_2_s0/CLK |
| 32.821 | -0.035 | tUnc | Number_d0_2_s0 | ||
| 32.770 | -0.051 | tSu | 1 | Number_d0_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.150, 32.895%; tC2Q: 0.306, 67.105% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
Path 5
Path Summary:| Slack | 1.458 |
| Data Arrival Time | 31.312 |
| Data Required Time | 32.770 |
| From | cmd_rx_0/DataNum_3_s0 |
| To | Number_d0_3_s0 |
| Launch Clk | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | pll_100M/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 30.706 | 0.706 | tCL | RR | 876 | pll_100M/PLLA_inst/CLKOUT0 |
| 30.856 | 0.150 | tNET | RR | 1 | cmd_rx_0/DataNum_3_s0/CLK |
| 31.162 | 0.306 | tC2Q | RR | 5 | cmd_rx_0/DataNum_3_s0/Q |
| 31.312 | 0.150 | tNET | RR | 1 | Number_d0_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 32.000 | 0.000 | eth_pll/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 32.706 | 0.706 | tCL | RR | 749 | eth_pll/PLLA_inst/CLKOUT0 |
| 32.856 | 0.150 | tNET | RR | 1 | Number_d0_3_s0/CLK |
| 32.821 | -0.035 | tUnc | Number_d0_3_s0 | ||
| 32.770 | -0.051 | tSu | 1 | Number_d0_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 2.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.150, 32.895%; tC2Q: 0.306, 67.105% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.150, 100.000% |