Timing Messages

Report Title	Timing Analysis Report
Design File	H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\impl\gwsynthesis\ad7606_ddr3_rgmii.vg
Physical Constraints File	H:\01_gaoyun\01_gao_project\ch59_ad7606_ddr3_rgmii\src\ad7606_ddr3_rgmii.cst
Timing Constraint File	---
Tool Version	V1.9.9 (64-bit)
Part Number	GW5A-LV25UG324C2/I1
Device	GW5A-25
Device Version	A
Created Time	Thu Feb 6 13:41:48 2025
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.85V -40C C2/I1
Hold Delay Model	Fast 0.95V 100C C2/I1
Numbers of Paths Analyzed	25306
Numbers of Endpoints Analyzed	18929
Numbers of Falling Endpoints	70
Numbers of Setup Violated Endpoints	40
Numbers of Hold Violated Endpoints	43

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
clk50m	Base	20.000	50.000	10.000			clk50m_ibuf/I
rgmii_rx_clk_i	Base	8.000	125.000	4.000			rgmii_rx_clk_i_ibuf/I
tck_pad_i	Base	50.000	20.000	25.000			gw_gao_inst_0/tck_ibuf/I
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Generated	5.000	200.000	2.500	clk50m_ibuf/I	clk50m	Gowin_PLL/PLLA_inst/CLKOUT1
pll_100M/PLLA_inst/CLKOUT0.default_gen_clk	Generated	10.000	100.000	5.000	clk50m_ibuf/I	clk50m	pll_100M/PLLA_inst/CLKOUT0
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	8.000	125.000	4.000	rgmii_rx_clk_i_ibuf/I	rgmii_rx_clk_i	eth_pll/PLLA_inst/CLKOUT0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Generated	20.000	50.000	10.000	Gowin_PLL/PLLA_inst/CLKOUT1	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk50m	50.000(MHz)	335.233(MHz)	6	TOP
2	tck_pad_i	20.000(MHz)	80.758(MHz)	7	TOP
3	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	200.000(MHz)	2338.896(MHz)	1	TOP
4	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk	100.000(MHz)	104.660(MHz)	9	TOP
5	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	125.000(MHz)	138.112(MHz)	11	TOP
6	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	50.000(MHz)	114.728(MHz)	10	TOP

No timing paths to get frequency of rgmii_rx_clk_i!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk50m	Setup	0.000	0
clk50m	Hold	0.000	0
rgmii_rx_clk_i	Setup	0.000	0
rgmii_rx_clk_i	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0
pll_100M/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
pll_100M/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Setup	0.000	0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-2.362	cmd_rx_0/DataNum_13_s0/Q	Number_d0_13_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.451	3.825
2	-1.965	cmd_rx_0/DataNum_15_s0/Q	Number_d0_15_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.507	3.372
3	-1.901	cmd_rx_0/DataNum_17_s0/Q	Number_d0_17_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.500	3.315
4	-1.786	cmd_rx_0/DataNum_6_s0/Q	Number_d0_6_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.510	3.190
5	-1.424	cmd_rx_0/DataNum_8_s0/Q	Number_d0_8_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.470	2.868
6	-1.403	cmd_rx_0/DataNum_16_s0/Q	Number_d0_16_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.500	2.817
7	-1.339	cmd_rx_0/DataNum_30_s0/Q	Number_d0_30_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.517	2.736
8	-1.276	cmd_rx_0/DataNum_11_s0/Q	Number_d0_11_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.478	2.712
9	-1.264	cmd_rx_0/DataNum_14_s0/Q	Number_d0_14_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.518	2.660
10	-1.161	cmd_rx_0/RestartReq_s1/Q	RestartReq_0_d0_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.491	2.584
11	-1.129	cmd_rx_0/DataNum_12_s0/Q	Number_d0_12_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.449	2.594
12	-1.095	cmd_rx_0/DataNum_5_s0/Q	Number_d0_5_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.526	2.483
13	-1.036	cmd_rx_0/DataNum_20_s0/Q	Number_d0_20_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.464	2.486
14	-0.934	cmd_rx_0/DataNum_18_s0/Q	Number_d0_18_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.487	2.361
15	-0.888	cmd_rx_0/DataNum_3_s0/Q	Number_d0_3_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.490	2.312
16	-0.798	cmd_rx_0/DataNum_4_s0/Q	Number_d0_4_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.486	2.226
17	-0.739	cmd_rx_0/DataNum_19_s0/Q	Number_d0_19_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.470	2.188
18	-0.731	cmd_rx_0/DataNum_26_s0/Q	Number_d0_26_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.481	2.164
19	-0.724	cmd_rx_0/DataNum_29_s0/Q	Number_d0_29_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.510	2.128
20	-0.650	cmd_rx_0/DataNum_1_s0/Q	Number_d0_1_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.492	2.072
21	-0.636	cmd_rx_0/DataNum_21_s0/Q	Number_d0_21_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.516	2.034
22	-0.629	cmd_rx_0/DataNum_9_s0/Q	Number_d0_9_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.483	2.060
23	-0.620	cmd_rx_0/DataNum_0_s0/Q	Number_d0_0_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.492	2.042
24	-0.614	cmd_rx_0/DataNum_10_s0/Q	Number_d0_10_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	2.000	0.498	2.030
25	-0.576	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	5.000	0.035	5.454

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	-0.401	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[3]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.559	0.243
2	-0.399	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[2]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.551	0.237
3	-0.393	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[1]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.551	0.243
4	-0.371	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	tck_pad_i:[R]	-0.784	0.449
5	-0.351	fifo_rx/fifo_inst/Equal.wptr_3_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/DI[3]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.503	0.237
6	-0.351	fifo_rx/fifo_inst/Equal.wptr_6_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[2]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.503	0.237
7	-0.345	fifo_rx/fifo_inst/Equal.wptr_0_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/DI[0]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.503	0.243
8	-0.309	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.563	0.339
9	-0.303	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[1]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.567	0.349
10	-0.297	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[3]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.555	0.343
11	-0.244	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.567	0.408
12	-0.228	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[2]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.567	0.424
13	-0.226	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.559	0.418
14	-0.215	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/Q	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[1]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.559	0.429
15	-0.175	fifo_tx/fifo_inst/Small.rptr_4_s0/Q	fifo_tx/fifo_inst/Small.wq1_rptr_4_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.499	0.360
16	-0.175	fifo_tx/fifo_inst/Small.rptr_7_s0/Q	fifo_tx/fifo_inst/Small.wq1_rptr_7_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.499	0.360
17	-0.175	fifo_tx/fifo_inst/Small.rptr_8_s0/Q	fifo_tx/fifo_inst/Small.wq1_rptr_8_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.499	0.360
18	-0.150	fifo_rx/fifo_inst/Equal.wptr_7_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[3]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.494	0.429
19	-0.150	fifo_rx/fifo_inst/Equal.wptr_2_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/DI[2]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.494	0.429
20	-0.143	fifo_rx/fifo_inst/Equal.wptr_5_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[1]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.493	0.435
21	-0.143	fifo_rx/fifo_inst/Equal.wptr_4_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[0]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.493	0.435
22	-0.138	fifo_rx/fifo_inst/Equal.wptr_8_s0/Q	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s12/DI[0]	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.496	0.443
23	-0.138	fifo_tx/fifo_inst/Small.rptr_1_s0/Q	fifo_tx/fifo_inst/Small.wq1_rptr_1_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.503	0.401
24	-0.138	fifo_tx/fifo_inst/Small.rptr_6_s0/Q	fifo_tx/fifo_inst/Small.wq1_rptr_6_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.503	0.401
25	-0.134	fifo_tx/fifo_inst/Small.rptr_0_s0/Q	fifo_tx/fifo_inst/Small.wq1_rptr_0_s0/D	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]	-0.499	0.401

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.062	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
2	0.062	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
3	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
4	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
5	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
6	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
7	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
8	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
9	0.351	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	2.500	-0.687	2.670
10	2.558	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
11	2.558	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
12	2.847	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
13	2.847	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
14	2.847	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
15	2.847	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
16	2.847	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
17	2.847	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	5.000	-0.685	2.670
18	16.839	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.027	2.670
19	16.839	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.027	2.670
20	17.129	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.034	2.670
21	17.136	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.027	2.670
22	17.136	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.027	2.670
23	17.136	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.027	2.670
24	17.136	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.027	2.670
25	17.144	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	20.000	0.019	2.670

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.271	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.977	1.415
2	0.271	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.977	1.415
3	0.347	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.900	1.415
4	0.347	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.900	1.415
5	0.347	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.900	1.415
6	0.347	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.900	1.415
7	0.347	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.900	1.415
8	0.588	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.660	1.415
9	0.588	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.660	1.415
10	0.588	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.660	1.415
11	0.588	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.660	1.415
12	0.588	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.660	1.415
13	0.588	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]	0.000	-0.660	1.415
14	1.273	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.025	1.415
15	1.277	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.029	1.415
16	1.277	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.029	1.415
17	1.277	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.029	1.415
18	1.281	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.033	1.415
19	1.281	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.033	1.415
20	2.744	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-1.006	1.415
21	2.744	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-1.006	1.415
22	2.830	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.920	1.415
23	2.830	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.920	1.415
24	2.830	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.920	1.415
25	2.830	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET	clk50m:[R]	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]	-2.500	-0.920	1.415

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.737	3.599	0.862	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
2	2.737	3.599	0.862	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
3	2.739	3.601	0.862	High Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s
4	2.739	3.601	0.862	High Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s
5	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Number_d0_12_s0
6	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Number_d1_13_s0
7	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Number_d1_12_s0
8	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_tx_gmii/cnt_eth_header_3_s0
9	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	eth_udp_tx_gmii/cnt_eth_header_1_s0
10	3.395	3.595	0.200	Low Pulse Width	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk	Number_d0_13_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-2.362
Data Arrival Time	35.592
Data Required Time	33.230
From	cmd_rx_0/DataNum_13_s0
To	Number_d0_13_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.767	0.686	tNET	RR	1	R32C22[0][B]	cmd_rx_0/DataNum_13_s0/CLK
32.073	0.306	tC2Q	RR	10	R32C22[0][B]	cmd_rx_0/DataNum_13_s0/Q
35.592	3.519	tNET	RR	1	R2C28[1][A]	Number_d0_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.316	0.730	tNET	RR	1	R2C28[1][A]	Number_d0_13_s0/CLK
33.281	-0.035	tUnc				Number_d0_13_s0
33.230	-0.051	tSu		1	R2C28[1][A]	Number_d0_13_s0

Path Statistics:

Clock Skew	-0.451
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.519, 92.000%; tC2Q: 0.306, 8.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.730, 100.000%

Path2

Path Summary:

Slack	-1.965
Data Arrival Time	35.159
Data Required Time	33.194
From	cmd_rx_0/DataNum_15_s0
To	Number_d0_15_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.787	0.705	tNET	RR	1	R25C23[2][B]	cmd_rx_0/DataNum_15_s0/CLK
32.093	0.306	tC2Q	RR	7	R25C23[2][B]	cmd_rx_0/DataNum_15_s0/Q
35.159	3.066	tNET	RR	1	R9C34[0][A]	Number_d0_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.280	0.693	tNET	RR	1	R9C34[0][A]	Number_d0_15_s0/CLK
33.245	-0.035	tUnc				Number_d0_15_s0
33.194	-0.051	tSu		1	R9C34[0][A]	Number_d0_15_s0

Path Statistics:

Clock Skew	-0.507
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.705, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.066, 90.925%; tC2Q: 0.306, 9.075%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.693, 100.000%

Path3

Path Summary:

Slack	-1.901
Data Arrival Time	35.095
Data Required Time	33.194
From	cmd_rx_0/DataNum_17_s0
To	Number_d0_17_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.780	0.698	tNET	RR	1	R33C21[1][B]	cmd_rx_0/DataNum_17_s0/CLK
32.086	0.306	tC2Q	RR	7	R33C21[1][B]	cmd_rx_0/DataNum_17_s0/Q
35.095	3.009	tNET	RR	1	R9C34[2][A]	Number_d0_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.280	0.693	tNET	RR	1	R9C34[2][A]	Number_d0_17_s0/CLK
33.245	-0.035	tUnc				Number_d0_17_s0
33.194	-0.051	tSu		1	R9C34[2][A]	Number_d0_17_s0

Path Statistics:

Clock Skew	-0.500
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.009, 90.769%; tC2Q: 0.306, 9.231%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.693, 100.000%

Path4

Path Summary:

Slack	-1.786
Data Arrival Time	34.977
Data Required Time	33.191
From	cmd_rx_0/DataNum_6_s0
To	Number_d0_6_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.787	0.705	tNET	RR	1	R25C23[3][A]	cmd_rx_0/DataNum_6_s0/CLK
32.093	0.306	tC2Q	RR	7	R25C23[3][A]	cmd_rx_0/DataNum_6_s0/Q
34.977	2.884	tNET	RR	1	R15C31[2][A]	Number_d0_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.277	0.691	tNET	RR	1	R15C31[2][A]	Number_d0_6_s0/CLK
33.242	-0.035	tUnc				Number_d0_6_s0
33.191	-0.051	tSu		1	R15C31[2][A]	Number_d0_6_s0

Path Statistics:

Clock Skew	-0.510
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.705, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.884, 90.408%; tC2Q: 0.306, 9.592%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%

Path5

Path Summary:

Slack	-1.424
Data Arrival Time	34.626
Data Required Time	33.201
From	cmd_rx_0/DataNum_8_s0
To	Number_d0_8_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.758	0.676	tNET	RR	1	R30C20[1][B]	cmd_rx_0/DataNum_8_s0/CLK
32.064	0.306	tC2Q	RR	7	R30C20[1][B]	cmd_rx_0/DataNum_8_s0/Q
34.626	2.562	tNET	RR	1	R17C32[2][A]	Number_d0_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.287	0.701	tNET	RR	1	R17C32[2][A]	Number_d0_8_s0/CLK
33.252	-0.035	tUnc				Number_d0_8_s0
33.201	-0.051	tSu		1	R17C32[2][A]	Number_d0_8_s0

Path Statistics:

Clock Skew	-0.470
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.562, 89.331%; tC2Q: 0.306, 10.669%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path6

Path Summary:

Slack	-1.403
Data Arrival Time	34.597
Data Required Time	33.194
From	cmd_rx_0/DataNum_16_s0
To	Number_d0_16_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.780	0.698	tNET	RR	1	R33C21[2][A]	cmd_rx_0/DataNum_16_s0/CLK
32.086	0.306	tC2Q	RR	8	R33C21[2][A]	cmd_rx_0/DataNum_16_s0/Q
34.597	2.511	tNET	RR	1	R9C34[1][A]	Number_d0_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.280	0.693	tNET	RR	1	R9C34[1][A]	Number_d0_16_s0/CLK
33.245	-0.035	tUnc				Number_d0_16_s0
33.194	-0.051	tSu		1	R9C34[1][A]	Number_d0_16_s0

Path Statistics:

Clock Skew	-0.500
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.511, 89.137%; tC2Q: 0.306, 10.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.693, 100.000%

Path7

Path Summary:

Slack	-1.339
Data Arrival Time	34.532
Data Required Time	33.192
From	cmd_rx_0/DataNum_30_s0
To	Number_d0_30_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.796	0.714	tNET	RR	1	R26C25[2][A]	cmd_rx_0/DataNum_30_s0/CLK
32.102	0.306	tC2Q	RR	7	R26C25[2][A]	cmd_rx_0/DataNum_30_s0/Q
34.532	2.430	tNET	RR	1	R16C31[3][A]	Number_d0_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.278	0.692	tNET	RR	1	R16C31[3][A]	Number_d0_30_s0/CLK
33.243	-0.035	tUnc				Number_d0_30_s0
33.192	-0.051	tSu		1	R16C31[3][A]	Number_d0_30_s0

Path Statistics:

Clock Skew	-0.517
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.714, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.430, 88.816%; tC2Q: 0.306, 11.184%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path8

Path Summary:

Slack	-1.276
Data Arrival Time	34.477
Data Required Time	33.201
From	cmd_rx_0/DataNum_11_s0
To	Number_d0_11_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.765	0.684	tNET	RR	1	R30C25[0][B]	cmd_rx_0/DataNum_11_s0/CLK
32.071	0.306	tC2Q	RR	7	R30C25[0][B]	cmd_rx_0/DataNum_11_s0/Q
34.477	2.406	tNET	RR	1	R9C33[0][A]	Number_d0_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.287	0.701	tNET	RR	1	R9C33[0][A]	Number_d0_11_s0/CLK
33.252	-0.035	tUnc				Number_d0_11_s0
33.201	-0.051	tSu		1	R9C33[0][A]	Number_d0_11_s0

Path Statistics:

Clock Skew	-0.478
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.406, 88.717%; tC2Q: 0.306, 11.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path9

Path Summary:

Slack	-1.264
Data Arrival Time	34.454
Data Required Time	33.190
From	cmd_rx_0/DataNum_14_s0
To	Number_d0_14_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.794	0.712	tNET	RR	1	R25C22[1][A]	cmd_rx_0/DataNum_14_s0/CLK
32.100	0.306	tC2Q	RR	8	R25C22[1][A]	cmd_rx_0/DataNum_14_s0/Q
34.454	2.354	tNET	RR	1	R11C33[0][B]	Number_d0_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.276	0.689	tNET	RR	1	R11C33[0][B]	Number_d0_14_s0/CLK
33.241	-0.035	tUnc				Number_d0_14_s0
33.190	-0.051	tSu		1	R11C33[0][B]	Number_d0_14_s0

Path Statistics:

Clock Skew	-0.518
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.712, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.354, 88.496%; tC2Q: 0.306, 11.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.689, 100.000%

Path10

Path Summary:

Slack	-1.161
Data Arrival Time	34.356
Data Required Time	33.195
From	cmd_rx_0/RestartReq_s1
To	RestartReq_0_d0_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.772	0.691	tNET	RR	1	R33C18[3][A]	cmd_rx_0/RestartReq_s1/CLK
32.078	0.306	tC2Q	RR	4	R33C18[3][A]	cmd_rx_0/RestartReq_s1/Q
34.356	2.278	tNET	RR	1	R18C31[1][A]	RestartReq_0_d0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.281	0.695	tNET	RR	1	R18C31[1][A]	RestartReq_0_d0_s0/CLK
33.246	-0.035	tUnc				RestartReq_0_d0_s0
33.195	-0.051	tSu		1	R18C31[1][A]	RestartReq_0_d0_s0

Path Statistics:

Clock Skew	-0.491
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.278, 88.158%; tC2Q: 0.306, 11.842%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%

Path11

Path Summary:

Slack	-1.129
Data Arrival Time	34.359
Data Required Time	33.230
From	cmd_rx_0/DataNum_12_s0
To	Number_d0_12_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.765	0.684	tNET	RR	1	R30C21[1][A]	cmd_rx_0/DataNum_12_s0/CLK
32.071	0.306	tC2Q	RR	6	R30C21[1][A]	cmd_rx_0/DataNum_12_s0/Q
34.359	2.288	tNET	RR	1	R2C28[0][A]	Number_d0_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.316	0.730	tNET	RR	1	R2C28[0][A]	Number_d0_12_s0/CLK
33.281	-0.035	tUnc				Number_d0_12_s0
33.230	-0.051	tSu		1	R2C28[0][A]	Number_d0_12_s0

Path Statistics:

Clock Skew	-0.449
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.288, 88.204%; tC2Q: 0.306, 11.796%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.730, 100.000%

Path12

Path Summary:

Slack	-1.095
Data Arrival Time	34.277
Data Required Time	33.182
From	cmd_rx_0/DataNum_5_s0
To	Number_d0_5_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.794	0.712	tNET	RR	1	R25C24[2][B]	cmd_rx_0/DataNum_5_s0/CLK
32.100	0.306	tC2Q	RR	9	R25C24[2][B]	cmd_rx_0/DataNum_5_s0/Q
34.277	2.177	tNET	RR	1	R11C30[0][A]	Number_d0_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.268	0.682	tNET	RR	1	R11C30[0][A]	Number_d0_5_s0/CLK
33.233	-0.035	tUnc				Number_d0_5_s0
33.182	-0.051	tSu		1	R11C30[0][A]	Number_d0_5_s0

Path Statistics:

Clock Skew	-0.526
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.712, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.177, 87.676%; tC2Q: 0.306, 12.324%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path13

Path Summary:

Slack	-1.036
Data Arrival Time	34.236
Data Required Time	33.200
From	cmd_rx_0/DataNum_20_s0
To	Number_d0_20_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.750	0.669	tNET	RR	1	R30C19[3][A]	cmd_rx_0/DataNum_20_s0/CLK
32.056	0.306	tC2Q	RR	5	R30C19[3][A]	cmd_rx_0/DataNum_20_s0/Q
34.236	2.180	tNET	RR	1	R16C28[1][A]	Number_d0_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.286	0.699	tNET	RR	1	R16C28[1][A]	Number_d0_20_s0/CLK
33.251	-0.035	tUnc				Number_d0_20_s0
33.200	-0.051	tSu		1	R16C28[1][A]	Number_d0_20_s0

Path Statistics:

Clock Skew	-0.464
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.180, 87.691%; tC2Q: 0.306, 12.309%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.699, 100.000%

Path14

Path Summary:

Slack	-0.934
Data Arrival Time	34.119
Data Required Time	33.185
From	cmd_rx_0/DataNum_18_s0
To	Number_d0_18_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.758	0.676	tNET	RR	1	R30C20[0][B]	cmd_rx_0/DataNum_18_s0/CLK
32.064	0.306	tC2Q	RR	6	R30C20[0][B]	cmd_rx_0/DataNum_18_s0/Q
34.119	2.055	tNET	RR	1	R16C30[1][A]	Number_d0_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.271	0.684	tNET	RR	1	R16C30[1][A]	Number_d0_18_s0/CLK
33.236	-0.035	tUnc				Number_d0_18_s0
33.185	-0.051	tSu		1	R16C30[1][A]	Number_d0_18_s0

Path Statistics:

Clock Skew	-0.487
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.055, 87.039%; tC2Q: 0.306, 12.961%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%

Path15

Path Summary:

Slack	-0.888
Data Arrival Time	34.062
Data Required Time	33.174
From	cmd_rx_0/DataNum_3_s0
To	Number_d0_3_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.750	0.669	tNET	RR	1	R30C19[1][A]	cmd_rx_0/DataNum_3_s0/CLK
32.056	0.306	tC2Q	RR	5	R30C19[1][A]	cmd_rx_0/DataNum_3_s0/Q
34.062	2.006	tNET	RR	1	R13C30[0][B]	Number_d0_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.260	0.674	tNET	RR	1	R13C30[0][B]	Number_d0_3_s0/CLK
33.225	-0.035	tUnc				Number_d0_3_s0
33.174	-0.051	tSu		1	R13C30[0][B]	Number_d0_3_s0

Path Statistics:

Clock Skew	-0.490
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.006, 86.765%; tC2Q: 0.306, 13.235%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.674, 100.000%

Path16

Path Summary:

Slack	-0.798
Data Arrival Time	33.984
Data Required Time	33.186
From	cmd_rx_0/DataNum_4_s0
To	Number_d0_4_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.758	0.676	tNET	RR	1	R30C26[1][A]	cmd_rx_0/DataNum_4_s0/CLK
32.064	0.306	tC2Q	RR	11	R30C26[1][A]	cmd_rx_0/DataNum_4_s0/Q
33.984	1.920	tNET	RR	1	R14C31[0][B]	Number_d0_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.272	0.686	tNET	RR	1	R14C31[0][B]	Number_d0_4_s0/CLK
33.237	-0.035	tUnc				Number_d0_4_s0
33.186	-0.051	tSu		1	R14C31[0][B]	Number_d0_4_s0

Path Statistics:

Clock Skew	-0.486
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.920, 86.253%; tC2Q: 0.306, 13.747%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%

Path17

Path Summary:

Slack	-0.739
Data Arrival Time	33.938
Data Required Time	33.199
From	cmd_rx_0/DataNum_19_s0
To	Number_d0_19_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.750	0.669	tNET	RR	1	R30C19[2][B]	cmd_rx_0/DataNum_19_s0/CLK
32.044	0.294	tC2Q	RF	7	R30C19[2][B]	cmd_rx_0/DataNum_19_s0/Q
33.938	1.894	tNET	FF	1	R17C29[3][A]	Number_d0_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.280	0.694	tNET	RR	1	R17C29[3][A]	Number_d0_19_s0/CLK
33.245	-0.035	tUnc				Number_d0_19_s0
33.199	-0.046	tSu		1	R17C29[3][A]	Number_d0_19_s0

Path Statistics:

Clock Skew	-0.470
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.894, 86.563%; tC2Q: 0.294, 13.437%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.694, 100.000%

Path18

Path Summary:

Slack	-0.731
Data Arrival Time	33.929
Data Required Time	33.198
From	cmd_rx_0/DataNum_26_s0
To	Number_d0_26_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.765	0.684	tNET	RR	1	R30C21[1][B]	cmd_rx_0/DataNum_26_s0/CLK
32.071	0.306	tC2Q	RR	5	R30C21[1][B]	cmd_rx_0/DataNum_26_s0/Q
33.929	1.858	tNET	RR	1	R15C32[0][A]	Number_d0_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.284	0.698	tNET	RR	1	R15C32[0][A]	Number_d0_26_s0/CLK
33.249	-0.035	tUnc				Number_d0_26_s0
33.198	-0.051	tSu		1	R15C32[0][A]	Number_d0_26_s0

Path Statistics:

Clock Skew	-0.481
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.858, 85.860%; tC2Q: 0.306, 14.140%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%

Path19

Path Summary:

Slack	-0.724
Data Arrival Time	33.908
Data Required Time	33.183
From	cmd_rx_0/DataNum_29_s0
To	Number_d0_29_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.780	0.698	tNET	RR	1	R33C21[3][A]	cmd_rx_0/DataNum_29_s0/CLK
32.086	0.306	tC2Q	RR	7	R33C21[3][A]	cmd_rx_0/DataNum_29_s0/Q
33.908	1.822	tNET	RR	1	R15C30[1][A]	Number_d0_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.269	0.683	tNET	RR	1	R15C30[1][A]	Number_d0_29_s0/CLK
33.234	-0.035	tUnc				Number_d0_29_s0
33.183	-0.051	tSu		1	R15C30[1][A]	Number_d0_29_s0

Path Statistics:

Clock Skew	-0.510
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.822, 85.620%; tC2Q: 0.306, 14.380%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.683, 100.000%

Path20

Path Summary:

Slack	-0.650
Data Arrival Time	33.832
Data Required Time	33.181
From	cmd_rx_0/DataNum_1_s0
To	Number_d0_1_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.760	0.678	tNET	RR	1	R32C23[0][A]	cmd_rx_0/DataNum_1_s0/CLK
32.066	0.306	tC2Q	RR	7	R32C23[0][A]	cmd_rx_0/DataNum_1_s0/Q
33.832	1.766	tNET	RR	1	R13C29[0][B]	Number_d0_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.267	0.681	tNET	RR	1	R13C29[0][B]	Number_d0_1_s0/CLK
33.232	-0.035	tUnc				Number_d0_1_s0
33.181	-0.051	tSu		1	R13C29[0][B]	Number_d0_1_s0

Path Statistics:

Clock Skew	-0.492
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.766, 85.232%; tC2Q: 0.306, 14.768%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path21

Path Summary:

Slack	-0.636
Data Arrival Time	33.836
Data Required Time	33.200
From	cmd_rx_0/DataNum_21_s0
To	Number_d0_21_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.802	0.720	tNET	RR	1	R25C21[0][A]	cmd_rx_0/DataNum_21_s0/CLK
32.108	0.306	tC2Q	RR	5	R25C21[0][A]	cmd_rx_0/DataNum_21_s0/Q
33.836	1.728	tNET	RR	1	R16C32[1][A]	Number_d0_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.286	0.699	tNET	RR	1	R16C32[1][A]	Number_d0_21_s0/CLK
33.251	-0.035	tUnc				Number_d0_21_s0
33.200	-0.051	tSu		1	R16C32[1][A]	Number_d0_21_s0

Path Statistics:

Clock Skew	-0.516
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.728, 84.956%; tC2Q: 0.306, 15.044%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.699, 100.000%

Path22

Path Summary:

Slack	-0.629
Data Arrival Time	33.820
Data Required Time	33.191
From	cmd_rx_0/DataNum_9_s0
To	Number_d0_9_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.760	0.678	tNET	RR	1	R32C23[1][B]	cmd_rx_0/DataNum_9_s0/CLK
32.066	0.306	tC2Q	RR	6	R32C23[1][B]	cmd_rx_0/DataNum_9_s0/Q
33.820	1.754	tNET	RR	1	R15C31[3][A]	Number_d0_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.277	0.691	tNET	RR	1	R15C31[3][A]	Number_d0_9_s0/CLK
33.242	-0.035	tUnc				Number_d0_9_s0
33.191	-0.051	tSu		1	R15C31[3][A]	Number_d0_9_s0

Path Statistics:

Clock Skew	-0.483
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.754, 85.146%; tC2Q: 0.306, 14.854%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%

Path23

Path Summary:

Slack	-0.620
Data Arrival Time	33.802
Data Required Time	33.181
From	cmd_rx_0/DataNum_0_s0
To	Number_d0_0_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.760	0.678	tNET	RR	1	R32C23[0][B]	cmd_rx_0/DataNum_0_s0/CLK
32.066	0.306	tC2Q	RR	7	R32C23[0][B]	cmd_rx_0/DataNum_0_s0/Q
33.802	1.736	tNET	RR	1	R13C29[0][A]	Number_d0_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.267	0.681	tNET	RR	1	R13C29[0][A]	Number_d0_0_s0/CLK
33.232	-0.035	tUnc				Number_d0_0_s0
33.181	-0.051	tSu		1	R13C29[0][A]	Number_d0_0_s0

Path Statistics:

Clock Skew	-0.492
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.736, 85.015%; tC2Q: 0.306, 14.985%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path24

Path Summary:

Slack	-0.614
Data Arrival Time	33.795
Data Required Time	33.181
From	cmd_rx_0/DataNum_10_s0
To	Number_d0_10_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
31.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
31.765	0.684	tNET	RR	1	R30C25[0][A]	cmd_rx_0/DataNum_10_s0/CLK
32.071	0.306	tC2Q	RR	5	R30C25[0][A]	cmd_rx_0/DataNum_10_s0/Q
33.795	1.724	tNET	RR	1	R13C31[1][A]	Number_d0_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
32.000	32.000					active clock edge time
32.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
32.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
33.267	0.681	tNET	RR	1	R13C31[1][A]	Number_d0_10_s0/CLK
33.232	-0.035	tUnc				Number_d0_10_s0
33.181	-0.051	tSu		1	R13C31[1][A]	Number_d0_10_s0

Path Statistics:

Clock Skew	-0.498
Setup Relationship	2.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.724, 84.926%; tC2Q: 0.306, 15.074%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.681, 100.000%

Path25

Path Summary:

Slack	-0.576
Data Arrival Time	21.689
Data Required Time	21.114
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
Launch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
15.000	15.000					active clock edge time
15.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
16.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
16.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
16.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.972	0.738	tNET	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
17.322	0.350	tINS	RR	8	DDRDLLM_TL	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[4]
20.228	2.906	tNET	RR	2	R13C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/I0
20.673	0.445	tINS	RF	1	R13C44[2][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n208_s/COUT
20.673	0.000	tNET	FF	2	R13C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n207_s/CIN
20.713	0.040	tINS	FR	1	R13C44[2][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n207_s/COUT
20.713	0.000	tNET	RR	2	R13C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n206_s/CIN
20.753	0.040	tINS	RR	1	R13C45[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n206_s/COUT
20.753	0.000	tNET	RR	2	R13C45[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n205_s/CIN
20.990	0.237	tINS	RR	1	R13C45[0][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n205_s/SUM
21.268	0.278	tNET	RR	1	R12C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/I1
21.689	0.421	tINS	RR	1	R12C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/F
21.689	0.000	tNET	RR	1	R12C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.200	0.676	tNET	RR	1	R12C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/CLK
21.165	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
21.114	-0.051	tSu		1	R12C46[1][B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0

Path Statistics:

Clock Skew	-0.035
Setup Relationship	5.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.157, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.533, 28.105%; route: 3.184, 58.374%; tC2Q: 0.738, 13.521%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.401
Data Arrival Time	1.059
Data Required Time	1.461
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.816	0.293	tNET	RR	1	R33C56[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/CLK
0.960	0.144	tC2Q	RR	1	R33C56[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q
1.059	0.099	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.376	0.294	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
1.411	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
1.461	0.050	tHld		1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.559
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.293, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%

Path2

Path Summary:

Slack	-0.399
Data Arrival Time	1.058
Data Required Time	1.457
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.820	0.297	tNET	RR	1	R33C55[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/CLK
0.964	0.144	tC2Q	RR	1	R33C55[2][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/Q
1.057	0.093	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.372	0.290	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
1.407	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
1.457	0.050	tHld		1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.551
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%

Path3

Path Summary:

Slack	-0.393
Data Arrival Time	1.063
Data Required Time	1.457
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.820	0.297	tNET	RR	1	R33C55[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/CLK
0.964	0.144	tC2Q	RR	1	R33C55[2][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/Q
1.063	0.099	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.372	0.290	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
1.407	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
1.457	0.050	tHld		1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.551
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%

Path4

Path Summary:

Slack	-0.371
Data Arrival Time	51.812
Data Required Time	52.183
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
51.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
51.363	0.281	tNET	RR	1	R31C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
51.507	0.144	tC2Q	RR	40	R31C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
51.606	0.099	tNET	RR	1	R31C32[0][A]	gw_gao_inst_0/u_la0_top/n4388_s1/I2
51.812	0.206	tINS	RF	1	R31C32[0][A]	gw_gao_inst_0/u_la0_top/n4388_s1/F
51.812	0.000	tNET	FF	1	R31C32[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
50.581	0.581	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
50.581	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.162	0.581	tINS	RR	458	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.985	tNET	RR	1	R31C32[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
52.182	0.035	tUnc				gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
52.183	0.001	tHld		1	R31C32[0][A]	gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew	0.784
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay	cell: 0.206, 45.880%; route: 0.099, 22.049%; tC2Q: 0.144, 32.071%
Required Clock Path Delay	cell: 1.162, 54.119%; route: 0.985, 45.881%

Path5

Path Summary:

Slack	-0.351
Data Arrival Time	41.115
Data Required Time	41.466
From	fifo_rx/fifo_inst/Equal.wptr_3_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.878	0.292	tNET	RR	1	R17C22[0][B]	fifo_rx/fifo_inst/Equal.wptr_3_s0/CLK
41.022	0.144	tC2Q	RR	1	R17C22[0][B]	fifo_rx/fifo_inst/Equal.wptr_3_s0/Q
41.115	0.093	tNET	RR	1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.381	0.299	tNET	RR	1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/CLK
41.416	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8
41.466	0.050	tHld		1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.503
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path6

Path Summary:

Slack	-0.351
Data Arrival Time	41.114
Data Required Time	41.465
From	fifo_rx/fifo_inst/Equal.wptr_6_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.877	0.290	tNET	RR	1	R16C22[0][A]	fifo_rx/fifo_inst/Equal.wptr_6_s0/CLK
41.021	0.144	tC2Q	RR	1	R16C22[0][A]	fifo_rx/fifo_inst/Equal.wptr_6_s0/Q
41.114	0.093	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.380	0.298	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/CLK
41.415	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
41.465	0.050	tHld		1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.503
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.298, 100.000%

Path7

Path Summary:

Slack	-0.345
Data Arrival Time	41.121
Data Required Time	41.466
From	fifo_rx/fifo_inst/Equal.wptr_0_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.878	0.292	tNET	RR	1	R17C22[2][B]	fifo_rx/fifo_inst/Equal.wptr_0_s0/CLK
41.022	0.144	tC2Q	RR	1	R17C22[2][B]	fifo_rx/fifo_inst/Equal.wptr_0_s0/Q
41.121	0.099	tNET	RR	1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.381	0.299	tNET	RR	1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/CLK
41.416	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8
41.466	0.050	tHld		1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.503
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path8

Path Summary:

Slack	-0.309
Data Arrival Time	1.148
Data Required Time	1.457
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.808	0.285	tNET	RR	1	R32C53[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/CLK
0.952	0.144	tC2Q	RR	1	R32C53[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/Q
1.148	0.195	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.372	0.290	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
1.407	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
1.457	0.050	tHld		1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.563
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.285, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%

Path9

Path Summary:

Slack	-0.303
Data Arrival Time	1.158
Data Required Time	1.461
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.808	0.285	tNET	RR	1	R32C57[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/CLK
0.952	0.144	tC2Q	RR	1	R32C57[1][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/Q
1.158	0.205	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.376	0.294	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
1.411	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
1.461	0.050	tHld		1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.567
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.285, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%

Path10

Path Summary:

Slack	-0.297
Data Arrival Time	1.160
Data Required Time	1.457
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.816	0.293	tNET	RR	1	R33C56[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/CLK
0.960	0.144	tC2Q	RR	1	R33C56[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/Q
1.159	0.199	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.372	0.290	tNET	RR	1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
1.407	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
1.457	0.050	tHld		1	R34C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.555
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.293, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%

Path11

Path Summary:

Slack	-0.244
Data Arrival Time	1.216
Data Required Time	1.461
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.808	0.285	tNET	RR	1	R32C57[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/CLK
0.952	0.144	tC2Q	RR	1	R32C57[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q
1.216	0.264	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.376	0.294	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
1.411	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
1.461	0.050	tHld		1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.567
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.285, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 64.706%; tC2Q: 0.144, 35.294%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%

Path12

Path Summary:

Slack	-0.228
Data Arrival Time	1.232
Data Required Time	1.461
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.808	0.285	tNET	RR	1	R32C57[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/CLK
0.952	0.144	tC2Q	RR	1	R32C57[3][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/Q
1.232	0.280	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.376	0.294	tNET	RR	1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
1.411	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
1.461	0.050	tHld		1	R34C56	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.567
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.285, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 66.038%; tC2Q: 0.144, 33.962%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%

Path13

Path Summary:

Slack	-0.226
Data Arrival Time	1.232
Data Required Time	1.458
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.290	tNET	RR	1	R34C57[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/CLK
0.958	0.144	tC2Q	RR	1	R34C57[0][A]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q
1.232	0.274	tNET	RR	1	R35C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.373	0.292	tNET	RR	1	R35C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/CLK
1.408	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
1.458	0.050	tHld		1	R35C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12

Path Statistics:

Clock Skew	0.559
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 65.550%; tC2Q: 0.144, 34.450%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%

Path14

Path Summary:

Slack	-0.215
Data Arrival Time	1.243
Data Required Time	1.458
From	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0
To	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
Launch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.814	0.290	tNET	RR	1	R34C57[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/CLK
0.958	0.144	tC2Q	RR	6	R34C57[0][B]	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/Q
1.243	0.285	tNET	RR	1	R35C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
1.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
1.373	0.292	tNET	RR	1	R35C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/CLK
1.408	0.035	tUnc				ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
1.458	0.050	tHld		1	R35C55	ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12

Path Statistics:

Clock Skew	0.559
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%

Path15

Path Summary:

Slack	-0.175
Data Arrival Time	41.239
Data Required Time	41.414
From	fifo_tx/fifo_inst/Small.rptr_4_s0
To	fifo_tx/fifo_inst/Small.wq1_rptr_4_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.879	0.293	tNET	RR	1	R18C34[1][B]	fifo_tx/fifo_inst/Small.rptr_4_s0/CLK
41.020	0.141	tC2Q	RF	1	R18C34[1][B]	fifo_tx/fifo_inst/Small.rptr_4_s0/Q
41.239	0.219	tNET	FF	1	R18C34[2][B]	fifo_tx/fifo_inst/Small.wq1_rptr_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.378	0.297	tNET	RR	1	R18C34[2][B]	fifo_tx/fifo_inst/Small.wq1_rptr_4_s0/CLK
41.413	0.035	tUnc				fifo_tx/fifo_inst/Small.wq1_rptr_4_s0
41.414	0.001	tHld		1	R18C34[2][B]	fifo_tx/fifo_inst/Small.wq1_rptr_4_s0

Path Statistics:

Clock Skew	0.499
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.293, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.219, 60.833%; tC2Q: 0.141, 39.167%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.297, 100.000%

Path16

Path Summary:

Slack	-0.175
Data Arrival Time	41.238
Data Required Time	41.413
From	fifo_tx/fifo_inst/Small.rptr_7_s0
To	fifo_tx/fifo_inst/Small.wq1_rptr_7_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.878	0.292	tNET	RR	1	R17C34[1][B]	fifo_tx/fifo_inst/Small.rptr_7_s0/CLK
41.019	0.141	tC2Q	RF	1	R17C34[1][B]	fifo_tx/fifo_inst/Small.rptr_7_s0/Q
41.238	0.219	tNET	FF	1	R17C34[0][B]	fifo_tx/fifo_inst/Small.wq1_rptr_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.377	0.295	tNET	RR	1	R17C34[0][B]	fifo_tx/fifo_inst/Small.wq1_rptr_7_s0/CLK
41.412	0.035	tUnc				fifo_tx/fifo_inst/Small.wq1_rptr_7_s0
41.413	0.001	tHld		1	R17C34[0][B]	fifo_tx/fifo_inst/Small.wq1_rptr_7_s0

Path Statistics:

Clock Skew	0.499
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.219, 60.833%; tC2Q: 0.141, 39.167%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.295, 100.000%

Path17

Path Summary:

Slack	-0.175
Data Arrival Time	41.237
Data Required Time	41.412
From	fifo_tx/fifo_inst/Small.rptr_8_s0
To	fifo_tx/fifo_inst/Small.wq1_rptr_8_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.877	0.290	tNET	RR	1	R16C34[0][B]	fifo_tx/fifo_inst/Small.rptr_8_s0/CLK
41.018	0.141	tC2Q	RF	1	R16C34[0][B]	fifo_tx/fifo_inst/Small.rptr_8_s0/Q
41.237	0.219	tNET	FF	1	R16C34[1][B]	fifo_tx/fifo_inst/Small.wq1_rptr_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.376	0.294	tNET	RR	1	R16C34[1][B]	fifo_tx/fifo_inst/Small.wq1_rptr_8_s0/CLK
41.411	0.035	tUnc				fifo_tx/fifo_inst/Small.wq1_rptr_8_s0
41.412	0.001	tHld		1	R16C34[1][B]	fifo_tx/fifo_inst/Small.wq1_rptr_8_s0

Path Statistics:

Clock Skew	0.499
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.219, 60.833%; tC2Q: 0.141, 39.167%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%

Path18

Path Summary:

Slack	-0.150
Data Arrival Time	41.315
Data Required Time	41.465
From	fifo_rx/fifo_inst/Equal.wptr_7_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.886	0.299	tNET	RR	1	R17C24[1][A]	fifo_rx/fifo_inst/Equal.wptr_7_s0/CLK
41.030	0.144	tC2Q	RR	1	R17C24[1][A]	fifo_rx/fifo_inst/Equal.wptr_7_s0/Q
41.315	0.285	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.380	0.298	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/CLK
41.415	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
41.465	0.050	tHld		1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.494
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.298, 100.000%

Path19

Path Summary:

Slack	-0.150
Data Arrival Time	41.316
Data Required Time	41.466
From	fifo_rx/fifo_inst/Equal.wptr_2_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.887	0.301	tNET	RR	1	R18C24[2][B]	fifo_rx/fifo_inst/Equal.wptr_2_s0/CLK
41.031	0.144	tC2Q	RR	1	R18C24[2][B]	fifo_rx/fifo_inst/Equal.wptr_2_s0/Q
41.316	0.285	tNET	RR	1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.381	0.299	tNET	RR	1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8/CLK
41.416	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8
41.466	0.050	tHld		1	R17C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s8

Path Statistics:

Clock Skew	0.494
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path20

Path Summary:

Slack	-0.143
Data Arrival Time	41.322
Data Required Time	41.465
From	fifo_rx/fifo_inst/Equal.wptr_5_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.887	0.301	tNET	RR	1	R18C24[0][B]	fifo_rx/fifo_inst/Equal.wptr_5_s0/CLK
41.031	0.144	tC2Q	RR	1	R18C24[0][B]	fifo_rx/fifo_inst/Equal.wptr_5_s0/Q
41.322	0.291	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.380	0.298	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/CLK
41.415	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
41.465	0.050	tHld		1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.493
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.291, 66.897%; tC2Q: 0.144, 33.103%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.298, 100.000%

Path21

Path Summary:

Slack	-0.143
Data Arrival Time	41.322
Data Required Time	41.465
From	fifo_rx/fifo_inst/Equal.wptr_4_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.887	0.301	tNET	RR	1	R18C24[0][A]	fifo_rx/fifo_inst/Equal.wptr_4_s0/CLK
41.031	0.144	tC2Q	RR	1	R18C24[0][A]	fifo_rx/fifo_inst/Equal.wptr_4_s0/Q
41.322	0.291	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.380	0.298	tNET	RR	1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10/CLK
41.415	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10
41.465	0.050	tHld		1	R16C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s10

Path Statistics:

Clock Skew	0.493
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.291, 66.897%; tC2Q: 0.144, 33.103%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.298, 100.000%

Path22

Path Summary:

Slack	-0.138
Data Arrival Time	41.329
Data Required Time	41.467
From	fifo_rx/fifo_inst/Equal.wptr_8_s0
To	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s12
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.886	0.299	tNET	RR	1	R17C24[0][B]	fifo_rx/fifo_inst/Equal.wptr_8_s0/CLK
41.030	0.144	tC2Q	RR	5	R17C24[0][B]	fifo_rx/fifo_inst/Equal.wptr_8_s0/Q
41.329	0.299	tNET	RR	1	R18C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s12/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.382	0.301	tNET	RR	1	R18C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s12/CLK
41.417	0.035	tUnc				fifo_rx/fifo_inst/Equal.rq1_wptr_0_s12
41.467	0.050	tHld		1	R18C21	fifo_rx/fifo_inst/Equal.rq1_wptr_0_s12

Path Statistics:

Clock Skew	0.496
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.299, 67.494%; tC2Q: 0.144, 32.506%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.301, 100.000%

Path23

Path Summary:

Slack	-0.138
Data Arrival Time	41.279
Data Required Time	41.417
From	fifo_tx/fifo_inst/Small.rptr_1_s0
To	fifo_tx/fifo_inst/Small.wq1_rptr_1_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.878	0.292	tNET	RR	1	R17C34[2][A]	fifo_tx/fifo_inst/Small.rptr_1_s0/CLK
41.019	0.141	tC2Q	RF	1	R17C34[2][A]	fifo_tx/fifo_inst/Small.rptr_1_s0/Q
41.279	0.260	tNET	FF	1	R17C33[1][A]	fifo_tx/fifo_inst/Small.wq1_rptr_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.381	0.299	tNET	RR	1	R17C33[1][A]	fifo_tx/fifo_inst/Small.wq1_rptr_1_s0/CLK
41.416	0.035	tUnc				fifo_tx/fifo_inst/Small.wq1_rptr_1_s0
41.417	0.001	tHld		1	R17C33[1][A]	fifo_tx/fifo_inst/Small.wq1_rptr_1_s0

Path Statistics:

Clock Skew	0.503
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.292, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 64.838%; tC2Q: 0.141, 35.162%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.299, 100.000%

Path24

Path Summary:

Slack	-0.138
Data Arrival Time	41.278
Data Required Time	41.416
From	fifo_tx/fifo_inst/Small.rptr_6_s0
To	fifo_tx/fifo_inst/Small.wq1_rptr_6_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.877	0.290	tNET	RR	1	R16C34[2][B]	fifo_tx/fifo_inst/Small.rptr_6_s0/CLK
41.018	0.141	tC2Q	RF	1	R16C34[2][B]	fifo_tx/fifo_inst/Small.rptr_6_s0/Q
41.278	0.260	tNET	FF	1	R16C33[0][B]	fifo_tx/fifo_inst/Small.wq1_rptr_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.380	0.298	tNET	RR	1	R16C33[0][B]	fifo_tx/fifo_inst/Small.wq1_rptr_6_s0/CLK
41.415	0.035	tUnc				fifo_tx/fifo_inst/Small.wq1_rptr_6_s0
41.416	0.001	tHld		1	R16C33[0][B]	fifo_tx/fifo_inst/Small.wq1_rptr_6_s0

Path Statistics:

Clock Skew	0.503
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 64.838%; tC2Q: 0.141, 35.162%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.298, 100.000%

Path25

Path Summary:

Slack	-0.134
Data Arrival Time	41.278
Data Required Time	41.412
From	fifo_tx/fifo_inst/Small.rptr_0_s0
To	fifo_tx/fifo_inst/Small.wq1_rptr_0_s0
Launch Clk	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk	pll_100M/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
40.586	0.586	tCL	RR	751	PLL_L[0]	eth_pll/PLLA_inst/CLKOUT0
40.877	0.290	tNET	RR	1	R16C34[0][A]	fifo_tx/fifo_inst/Small.rptr_0_s0/CLK
41.018	0.141	tC2Q	RF	1	R16C34[0][A]	fifo_tx/fifo_inst/Small.rptr_0_s0/Q
41.278	0.260	tNET	FF	1	R16C34[1][A]	fifo_tx/fifo_inst/Small.wq1_rptr_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					pll_100M/PLLA_inst/CLKOUT0.default_gen_clk
41.082	1.082	tCL	RR	882	PLL_L[1]	pll_100M/PLLA_inst/CLKOUT0
41.376	0.294	tNET	RR	1	R16C34[1][A]	fifo_tx/fifo_inst/Small.wq1_rptr_0_s0/CLK
41.411	0.035	tUnc				fifo_tx/fifo_inst/Small.wq1_rptr_0_s0
41.412	0.001	tHld		1	R16C34[1][A]	fifo_tx/fifo_inst/Small.wq1_rptr_0_s0

Path Statistics:

Clock Skew	0.499
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.290, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 64.838%; tC2Q: 0.141, 35.162%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.294, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.062
Data Arrival Time	3.945
Data Required Time	4.006
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
4.006	-0.420	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path2

Path Summary:

Slack	0.062
Data Arrival Time	3.945
Data Required Time	4.006
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
4.006	-0.420	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path3

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
4.296	-0.130	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path4

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
4.296	-0.130	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path5

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
4.296	-0.130	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path6

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
4.296	-0.130	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path7

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
4.296	-0.130	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path8

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
4.296	-0.130	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path9

Path Summary:

Slack	0.351
Data Arrival Time	3.945
Data Required Time	4.296
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2.500	2.500					active clock edge time
2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
3.578	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
3.578	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.738	0.160	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
4.461	0.723	tNET	FF	1	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/FCLK
4.426	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
4.296	-0.130	tSu		1	IOT43[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen

Path Statistics:

Clock Skew	0.687
Setup Relationship	2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.160, 18.151%; route: 0.723, 81.849%

Path10

Path Summary:

Slack	2.558
Data Arrival Time	3.945
Data Required Time	6.503
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
6.503	-0.422	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path11

Path Summary:

Slack	2.558
Data Arrival Time	3.945
Data Required Time	6.503
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
6.503	-0.422	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path12

Path Summary:

Slack	2.847
Data Arrival Time	3.945
Data Required Time	6.792
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
6.792	-0.132	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path13

Path Summary:

Slack	2.847
Data Arrival Time	3.945
Data Required Time	6.792
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
6.792	-0.132	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path14

Path Summary:

Slack	2.847
Data Arrival Time	3.945
Data Required Time	6.792
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
6.792	-0.132	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path15

Path Summary:

Slack	2.847
Data Arrival Time	3.945
Data Required Time	6.792
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
6.792	-0.132	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path16

Path Summary:

Slack	2.847
Data Arrival Time	3.945
Data Required Time	6.792
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
6.792	-0.132	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path17

Path Summary:

Slack	2.847
Data Arrival Time	3.945
Data Required Time	6.792
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
6.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
6.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
6.235	0.157	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
6.959	0.725	tNET	RR	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
6.924	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
6.792	-0.132	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	0.685
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.157, 17.800%; route: 0.725, 82.200%

Path18

Path Summary:

Slack	16.839
Data Arrival Time	3.945
Data Required Time	20.784
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	10	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
20.784	-0.429	tSu		1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path19

Path Summary:

Slack	16.839
Data Arrival Time	3.945
Data Required Time	20.784
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	10	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
20.784	-0.429	tSu		1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path20

Path Summary:

Slack	17.129
Data Arrival Time	3.945
Data Required Time	21.074
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.240	0.717	tNET	RR	1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK
21.205	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
21.074	-0.132	tSu		1	IOT33[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew	-0.034
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path21

Path Summary:

Slack	17.136
Data Arrival Time	3.945
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
21.081	-0.132	tSu		1	IOT56[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path22

Path Summary:

Slack	17.136
Data Arrival Time	3.945
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
21.081	-0.132	tSu		1	IOT50[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path23

Path Summary:

Slack	17.136
Data Arrival Time	3.945
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
21.081	-0.132	tSu		1	IOT37[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path24

Path Summary:

Slack	17.136
Data Arrival Time	3.945
Data Required Time	21.081
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.248	0.725	tNET	RR	1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/PCLK
21.213	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
21.081	-0.132	tSu		1	IOT39[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew	-0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.725, 100.000%

Path25

Path Summary:

Slack	17.144
Data Arrival Time	3.945
Data Required Time	21.089
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.587	0.587	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
1.275	0.688	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.569	0.294	tC2Q	RF	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
3.945	2.376	tNET	FF	2	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.524	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
21.256	0.732	tNET	RR	1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK
21.221	-0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
21.089	-0.132	tSu		1	IOT31[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew	-0.019
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 46.046%; route: 0.688, 53.954%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.376, 88.990%; tC2Q: 0.294, 11.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.732, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.271
Data Arrival Time	2.288
Data Required Time	2.017
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.850	0.317	tINS	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.850	0.000	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.885	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
2.017	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.977
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.452, 58.495%; route: 0.321, 41.505%

Path2

Path Summary:

Slack	0.271
Data Arrival Time	2.288
Data Required Time	2.017
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.850	0.317	tINS	RR	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.850	0.000	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.885	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
2.017	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.977
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.452, 58.495%; route: 0.321, 41.505%

Path3

Path Summary:

Slack	0.347
Data Arrival Time	2.288
Data Required Time	1.940
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.773	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.773	0.000	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
1.808	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.940	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.900
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path4

Path Summary:

Slack	0.347
Data Arrival Time	2.288
Data Required Time	1.940
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.773	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.773	0.000	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
1.808	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.940	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.900
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path5

Path Summary:

Slack	0.347
Data Arrival Time	2.288
Data Required Time	1.940
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.773	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.773	0.000	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
1.808	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.940	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.900
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path6

Path Summary:

Slack	0.347
Data Arrival Time	2.288
Data Required Time	1.940
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.773	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.773	0.000	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
1.808	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.940	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.900
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path7

Path Summary:

Slack	0.347
Data Arrival Time	2.288
Data Required Time	1.940
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT76[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.773	0.240	tINS	RR	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.773	0.000	tNET	RR	1	IOT76[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TCLK
1.808	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
1.940	0.132	tHld		1	IOT76[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem

Path Statistics:

Clock Skew	0.900
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.375, 53.916%; route: 0.321, 46.084%

Path8

Path Summary:

Slack	0.588
Data Arrival Time	2.288
Data Required Time	1.700
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.568	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.700	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.660
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path9

Path Summary:

Slack	0.588
Data Arrival Time	2.288
Data Required Time	1.700
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
1.568	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.700	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	0.660
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path10

Path Summary:

Slack	0.588
Data Arrival Time	2.288
Data Required Time	1.700
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK
1.568	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.700	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.660
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path11

Path Summary:

Slack	0.588
Data Arrival Time	2.288
Data Required Time	1.700
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK
1.568	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.700	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.660
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path12

Path Summary:

Slack	0.588
Data Arrival Time	2.288
Data Required Time	1.700
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK
1.568	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.700	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.660
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path13

Path Summary:

Slack	0.588
Data Arrival Time	2.288
Data Required Time	1.700
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
1.078	1.078	tCL	RR	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
1.078	0.000	tNET	RR	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
1.212	0.134	tINS	RR	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
1.533	0.321	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK
1.568	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.700	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.660
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.134, 29.556%; route: 0.321, 70.444%

Path14

Path Summary:

Slack	1.273
Data Arrival Time	2.288
Data Required Time	1.015
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848	0.325	tNET	RR	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.883	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.015	0.132	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.325, 100.000%

Path15

Path Summary:

Slack	1.277
Data Arrival Time	2.288
Data Required Time	1.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.844	0.321	tNET	RR	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.879	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.011	0.132	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path16

Path Summary:

Slack	1.277
Data Arrival Time	2.288
Data Required Time	1.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.844	0.321	tNET	RR	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK
0.879	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.011	0.132	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	-0.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path17

Path Summary:

Slack	1.277
Data Arrival Time	2.288
Data Required Time	1.011
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.844	0.321	tNET	RR	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/PCLK
0.879	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.011	0.132	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	-0.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.321, 100.000%

Path18

Path Summary:

Slack	1.281
Data Arrival Time	2.288
Data Required Time	1.007
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.840	0.317	tNET	RR	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.875	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.007	0.132	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	-0.033
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path19

Path Summary:

Slack	1.281
Data Arrival Time	2.288
Data Required Time	1.007
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.523	0.523	tCL	RR	3238	TOPSIDE[0]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.840	0.317	tNET	RR	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
0.875	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.007	0.132	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	-0.033
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.317, 100.000%

Path20

Path Summary:

Slack	2.744
Data Arrival Time	2.288
Data Required Time	-0.456
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.422	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.422	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.282	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-0.956	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.621	0.335	tINS	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-0.621	0.000	tNET	FF	1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-0.586	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-0.456	0.130	tHld		1	IOT80[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	1.006
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.475, 59.299%; route: 0.326, 40.701%

Path21

Path Summary:

Slack	2.744
Data Arrival Time	2.288
Data Required Time	-0.456
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.422	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.422	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.282	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-0.956	0.326	tNET	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.621	0.335	tINS	FF	1	R0C60	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-0.621	0.000	tNET	FF	1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-0.586	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-0.456	0.130	tHld		1	IOT61[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew	1.006
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.475, 59.299%; route: 0.326, 40.701%

Path22

Path Summary:

Slack	2.830
Data Arrival Time	2.288
Data Required Time	-0.542
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.422	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.422	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.282	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-0.956	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.707	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.707	0.000	tNET	FF	1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
-0.672	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
-0.542	0.130	tHld		1	IOT85[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew	0.920
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Path23

Path Summary:

Slack	2.830
Data Arrival Time	2.288
Data Required Time	-0.542
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.422	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.422	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.282	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-0.956	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.707	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.707	0.000	tNET	FF	1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
-0.672	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
-0.542	0.130	tHld		1	IOT83[B]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew	0.920
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Path24

Path Summary:

Slack	2.830
Data Arrival Time	2.288
Data Required Time	-0.542
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.422	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.422	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.282	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-0.956	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.707	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.707	0.000	tNET	FF	1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
-0.672	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
-0.542	0.130	tHld		1	IOT83[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew	0.920
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Path25

Path Summary:

Slack	2.830
Data Arrival Time	2.288
Data Required Time	-0.542
From	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk	clk50m:[R]
Latch Clk	Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk50m
0.000	0.000	tCL	RR	1	IOB29[A]	clk50m_ibuf/I
0.581	0.581	tINS	RR	41	IOB29[A]	clk50m_ibuf/O
0.873	0.292	tNET	RR	1	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.017	0.144	tC2Q	RR	2196	R14C40[0][A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.288	1.271	tNET	RR	2	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-2.500	-2.500					active clock edge time
-2.500	0.000					Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk
-1.422	1.078	tCL	FF	1	PLL_B	Gowin_PLL/PLLA_inst/CLKOUT1
-1.422	0.000	tNET	FF	3	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.282	0.140	tINS	FF	64	-	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-0.956	0.326	tNET	FF	1	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-0.707	0.249	tINS	FF	9	R0C82	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-0.707	0.000	tNET	FF	1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
-0.672	0.035	tUnc				ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
-0.542	0.130	tHld		1	IOT76[A]	ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew	0.920
Hold Relationship	-2.500
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 66.549%; route: 0.292, 33.451%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.271, 89.822%; tC2Q: 0.144, 10.178%
Required Clock Path Delay	cell: 0.389, 54.390%; route: 0.326, 45.610%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.737
Actual Width:	3.599
Required Width:	0.862
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.286	0.700	tNET	FF	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.885	0.299	tNET	RR	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	2.737
Actual Width:	3.599
Required Width:	0.862
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.286	0.700	tNET	FF	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.885	0.299	tNET	RR	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW3

MPW Summary:

Slack:	2.739
Actual Width:	3.601
Required Width:	0.862
Type:	High Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
1.289	0.703	tNET	RR	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
4.890	0.304	tNET	FF	fifo_rx/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	2.739
Actual Width:	3.601
Required Width:	0.862
Type:	High Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
1.289	0.703	tNET	RR	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
4.890	0.304	tNET	FF	fifo_tx/fifo_inst/Small.mem_Small.mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	Number_d0_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	Number_d0_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	Number_d0_12_s0/CLK

MPW6

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	Number_d1_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	Number_d1_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	Number_d1_13_s0/CLK

MPW7

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	Number_d1_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	Number_d1_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	Number_d1_12_s0/CLK

MPW8

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_tx_gmii/cnt_eth_header_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_tx_gmii/cnt_eth_header_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_tx_gmii/cnt_eth_header_3_s0/CLK

MPW9

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	eth_udp_tx_gmii/cnt_eth_header_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	eth_udp_tx_gmii/cnt_eth_header_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	eth_udp_tx_gmii/cnt_eth_header_1_s0/CLK

MPW10

MPW Summary:

Slack:	3.395
Actual Width:	3.595
Required Width:	0.200
Type:	Low Pulse Width
Clock:	eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects:	Number_d0_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
4.586	0.586	tCL	FF	eth_pll/PLLA_inst/CLKOUT0
5.315	0.728	tNET	FF	Number_d0_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			eth_pll/PLLA_inst/CLKOUT0.default_gen_clk
8.586	0.586	tCL	RR	eth_pll/PLLA_inst/CLKOUT0
8.909	0.323	tNET	RR	Number_d0_13_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3238	ui_clk	0.176	0.732
2196	ui_clk_sync_rst	0.062	2.553
882	loc_clk100m	-2.362	0.730
751	gmii_tx_clk	0.760	0.732
458	control0[0]	4.532	1.880
389	eye_calib_start_Z	12.692	4.520
251	raddr[3]	12.515	2.065
221	led_d_12[1]	6.162	3.574
149	n20_3	45.533	2.517
148	dqsts1	17.497	1.698

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R10C59	65.28%
R28C47	63.89%
R28C43	61.11%
R10C56	61.11%
R28C44	59.72%
R28C51	59.72%
R28C59	59.72%
R10C65	59.72%
R10C72	59.72%
R12C47	58.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command