Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\01_gaoyun\gao_project\62_ad7606_ddr3_rgmii\09_01\src\fifo_rx\temp\FIFO\fifo_define.v H:\01_gaoyun\gao_project\62_ad7606_ddr3_rgmii\09_01\src\fifo_rx\temp\FIFO\fifo_parameter.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\edc.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Fri Sep 01 09:45:35 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | fifo_rx |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.486s, Peak memory usage = 38.852MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.852MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.852MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.852MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.852MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.852MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.852MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.852MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.852MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.852MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.852MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.852MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.294s, Peak memory usage = 44.012MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.012MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.012MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.764s, Elapsed time = 0h 0m 0.798s, Peak memory usage = 44.012MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 23 |
| I/O Buf | 23 |
| IBUF | 13 |
| OBUF | 10 |
| Register | 61 |
| DFFPE | 5 |
| DFFCE | 56 |
| LUT | 67 |
| LUT2 | 16 |
| LUT3 | 24 |
| LUT4 | 27 |
| ALU | 9 |
| ALU | 9 |
| SSRAM | 3 |
| RAM16S4 | 3 |
| INV | 4 |
| INV | 4 |
| BSRAM | 1 |
| SDPB | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 98(71 LUT, 9 ALU, 3 RAM16) / 23040 | <1% |
| Register | 61 / 23685 | <1% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 61 / 23685 | <1% |
| BSRAM | 1 / 56 | 2% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 | RdClk_ibuf/I | ||
| WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 | WrClk_ibuf/I | ||
| fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_inst/n4_s2/O | ||
| fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | fifo_inst/n9_s2/O |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | RdClk | 100.0(MHz) | 124.1(MHz) | 6 | TOP |
| 2 | WrClk | 100.0(MHz) | 305.1(MHz) | 5 | TOP |
| 3 | fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 4 | fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.945 |
| Data Arrival Time | 8.830 |
| Data Required Time | 10.776 |
| From | fifo_inst/Equal.rq1_wptr_0_s8 |
| To | fifo_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 4 | fifo_inst/Equal.rq1_wptr_0_s8/CLK |
| 6.239 | 5.376 | tC2Q | RR | 1 | fifo_inst/Equal.rq1_wptr_0_s8/DO[0] |
| 6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rq2_wptr_0_s4/I0 |
| 6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Equal.rq2_wptr_0_s4/F |
| 7.104 | 0.180 | tNET | RR | 1 | fifo_inst/n95_s0/I1 |
| 7.644 | 0.540 | tINS | RF | 1 | fifo_inst/n95_s0/COUT |
| 7.644 | 0.000 | tNET | FF | 1 | fifo_inst/n96_s0/CIN |
| 7.692 | 0.048 | tINS | FR | 1 | fifo_inst/n96_s0/COUT |
| 7.692 | 0.000 | tNET | RR | 1 | fifo_inst/n97_s0/CIN |
| 7.740 | 0.048 | tINS | RR | 1 | fifo_inst/n97_s0/COUT |
| 7.740 | 0.000 | tNET | RR | 1 | fifo_inst/n98_s0/CIN |
| 7.788 | 0.048 | tINS | RR | 1 | fifo_inst/n98_s0/COUT |
| 7.788 | 0.000 | tNET | RR | 1 | fifo_inst/n99_s0/CIN |
| 7.836 | 0.048 | tINS | RR | 1 | fifo_inst/n99_s0/COUT |
| 7.836 | 0.000 | tNET | RR | 1 | fifo_inst/n100_s0/CIN |
| 7.884 | 0.048 | tINS | RR | 1 | fifo_inst/n100_s0/COUT |
| 7.884 | 0.000 | tNET | RR | 1 | fifo_inst/n101_s0/CIN |
| 7.932 | 0.048 | tINS | RR | 1 | fifo_inst/n101_s0/COUT |
| 7.932 | 0.000 | tNET | RR | 1 | fifo_inst/n102_s0/CIN |
| 7.980 | 0.048 | tINS | RR | 1 | fifo_inst/n102_s0/COUT |
| 7.980 | 0.000 | tNET | RR | 1 | fifo_inst/n103_s0/CIN |
| 8.028 | 0.048 | tINS | RR | 2 | fifo_inst/n103_s0/COUT |
| 8.208 | 0.180 | tNET | RR | 1 | fifo_inst/n33_s1/I2 |
| 8.650 | 0.443 | tINS | RR | 1 | fifo_inst/n33_s1/F |
| 8.830 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.mem_Equal.mem_0_0_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
| 10.776 | -0.087 | tSu | 1 | fifo_inst/Equal.mem_Equal.mem_0_0_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.872, 23.494%; route: 0.720, 9.036%; tC2Q: 5.376, 67.470% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 6.660 |
| Data Arrival Time | 4.141 |
| Data Required Time | 10.801 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Equal.rptr_7_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
| 1.410 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s6/I0 |
| 1.915 | 0.505 | tINS | RR | 6 | fifo_inst/rbin_num_next_2_s6/F |
| 2.095 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_5_s7/I1 |
| 2.591 | 0.496 | tINS | RR | 7 | fifo_inst/rbin_num_next_5_s7/F |
| 2.771 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_7_s7/I0 |
| 3.276 | 0.505 | tINS | RR | 4 | fifo_inst/rbin_num_next_7_s7/F |
| 3.456 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_7_s0/I0 |
| 3.961 | 0.505 | tINS | RR | 2 | fifo_inst/Equal.rgraynext_7_s0/F |
| 4.141 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_7_s0/CLK |
| 10.801 | -0.061 | tSu | 1 | fifo_inst/Equal.rptr_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 6.723 |
| Data Arrival Time | 4.079 |
| Data Required Time | 10.801 |
| From | fifo_inst/Full_s0 |
| To | fifo_inst/Full_s0 |
| Launch Clk | WrClk[R] |
| Latch Clk | WrClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | WrClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 38 | WrClk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
| 1.230 | 0.367 | tC2Q | RR | 6 | fifo_inst/Full_s0/Q |
| 1.410 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_2_s1/I0 |
| 1.915 | 0.505 | tINS | RR | 15 | fifo_inst/Equal.wgraynext_2_s1/F |
| 2.095 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_7_s4/I1 |
| 2.591 | 0.496 | tINS | RR | 3 | fifo_inst/Equal.wbinnext_7_s4/F |
| 2.771 | 0.180 | tNET | RR | 1 | fifo_inst/wfull_val_s1/I2 |
| 3.213 | 0.443 | tINS | RR | 1 | fifo_inst/wfull_val_s1/F |
| 3.393 | 0.180 | tNET | RR | 1 | fifo_inst/wfull_val_s0/I0 |
| 3.899 | 0.505 | tINS | RR | 1 | fifo_inst/wfull_val_s0/F |
| 4.079 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | WrClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 38 | WrClk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
| 10.801 | -0.061 | tSu | 1 | fifo_inst/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.949, 60.597%; route: 0.900, 27.985%; tC2Q: 0.367, 11.418% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.732 |
| Data Arrival Time | 4.069 |
| Data Required Time | 10.801 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Equal.rptr_5_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
| 1.410 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s6/I0 |
| 1.915 | 0.505 | tINS | RR | 6 | fifo_inst/rbin_num_next_2_s6/F |
| 2.095 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_5_s7/I1 |
| 2.591 | 0.496 | tINS | RR | 7 | fifo_inst/rbin_num_next_5_s7/F |
| 2.771 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_6_s5/I1 |
| 3.266 | 0.496 | tINS | RR | 3 | fifo_inst/rbin_num_next_6_s5/F |
| 3.446 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_5_s1/I2 |
| 3.889 | 0.443 | tINS | RR | 2 | fifo_inst/Equal.rgraynext_5_s1/F |
| 4.069 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_5_s0/CLK |
| 10.801 | -0.061 | tSu | 1 | fifo_inst/Equal.rptr_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.939, 60.479%; route: 0.900, 28.069%; tC2Q: 0.367, 11.452% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.914 |
| Data Arrival Time | 3.888 |
| Data Required Time | 10.801 |
| From | fifo_inst/Empty_s0 |
| To | fifo_inst/Equal.rptr_6_s0 |
| Launch Clk | RdClk[R] |
| Latch Clk | RdClk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | RdClk | |||
| 0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
| 1.410 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_2_s6/I0 |
| 1.915 | 0.505 | tINS | RR | 6 | fifo_inst/rbin_num_next_2_s6/F |
| 2.095 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_5_s7/I1 |
| 2.591 | 0.496 | tINS | RR | 7 | fifo_inst/rbin_num_next_5_s7/F |
| 2.771 | 0.180 | tNET | RR | 1 | fifo_inst/rbin_num_next_7_s7/I0 |
| 3.276 | 0.505 | tINS | RR | 4 | fifo_inst/rbin_num_next_7_s7/F |
| 3.456 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_6_s1/I3 |
| 3.708 | 0.252 | tINS | RR | 2 | fifo_inst/Equal.rgraynext_6_s1/F |
| 3.888 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | RdClk | |||
| 10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 26 | RdClk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_6_s0/CLK |
| 10.801 | -0.061 | tSu | 1 | fifo_inst/Equal.rptr_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 1.758, 58.112%; route: 0.900, 29.750%; tC2Q: 0.367, 12.138% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |