Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Mon Aug 21 14:55:36 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR3_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 67.762MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 67.762MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 67.762MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 67.762MB Optimizing Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.362s, Peak memory usage = 67.762MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 67.762MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 67.762MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 67.762MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 67.762MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 67.762MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 67.762MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 67.762MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 73.805MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 73.805MB Generate output files: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 73.805MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 73.805MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 370 |
| I/O Buf | 364 |
| IBUF | 182 |
| OBUF | 161 |
| TBUF | 2 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 2980 |
| DFFSE | 1 |
| DFFRE | 701 |
| DFFPE | 62 |
| DFFCE | 2216 |
| LUT | 2370 |
| LUT2 | 380 |
| LUT3 | 1210 |
| LUT4 | 780 |
| ALU | 173 |
| ALU | 173 |
| INV | 28 |
| INV | 28 |
| IOLOGIC | 76 |
| IDES8_MEM | 16 |
| OSER8 | 24 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 12 |
| SDPB | 4 |
| SDPX9B | 8 |
| CLOCK | 5 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| DHCE | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2571(2398 LUT, 173 ALU) / 23040 | 12% |
| Register | 2980 / 23685 | 13% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 2980 / 23685 | 13% |
| BSRAM | 12 / 56 | 22% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
| gw3_top/u_ddr_phy_top/u_ddr_init/n1784_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw3_top/u_ddr_phy_top/u_ddr_init/n1784_s2/O | ||
| gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.0(MHz) | 1506.0(MHz) | 1 | TOP |
| 2 | clk | 100.0(MHz) | 253.6(MHz) | 6 | TOP |
| 3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 148.3(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.126 |
| Data Arrival Time | 1.565 |
| Data Required Time | 5.691 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.152 | 0.152 | tCL | RR | 3027 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.332 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
| 0.700 | 0.367 | tC2Q | RR | 11 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
| 0.880 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
| 1.385 | 0.505 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
| 1.565 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.856 | 0.168 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 6.042 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 6.210 | 0.168 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.175 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.691 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.877 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.505, 40.993%; route: 0.360, 29.211%; tC2Q: 0.367, 29.796% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | 4.126 |
| Data Arrival Time | 1.565 |
| Data Required Time | 5.691 |
| From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.152 | 0.152 | tCL | RR | 3027 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.332 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
| 0.700 | 0.367 | tC2Q | RR | 11 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
| 0.880 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
| 1.385 | 0.505 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
| 1.565 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.856 | 0.168 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 6.042 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 6.210 | 0.168 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.175 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.691 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.877 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.505, 40.993%; route: 0.360, 29.211%; tC2Q: 0.367, 29.796% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:| Slack | 4.229 |
| Data Arrival Time | 1.410 |
| Data Required Time | 5.639 |
| From | gw3_top/u_ddr_phy_top/stop_reg_2_s0 |
| To | gw3_top/u_ddr_phy_top/fclk_dhcen |
| Launch Clk | clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK |
| 1.230 | 0.367 | tC2Q | RR | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q |
| 1.410 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.856 | 0.168 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 5.821 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/fclk_dhcen | ||
| 5.639 | -0.182 | tSu | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen |
| Clock Skew: | -0.007 |
| Setup Relationship: | 5.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.180, 32.895%; tC2Q: 0.367, 67.105% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 5.779 |
| Data Arrival Time | 34.458 |
| Data Required Time | 40.236 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.683 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
| 30.862 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 31.230 | 0.367 | tC2Q | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 31.410 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/I3 |
| 31.662 | 0.252 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/F |
| 31.842 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/I2 |
| 32.285 | 0.443 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/F |
| 32.465 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/I2 |
| 32.907 | 0.443 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/F |
| 33.087 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I0 |
| 33.592 | 0.505 | tINS | RR | 16 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F |
| 33.772 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/I0 |
| 34.278 | 0.505 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/F |
| 34.458 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.152 | 0.152 | tCL | RR | 3027 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.332 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/CLK |
| 40.297 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 | ||
| 40.236 | -0.061 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0 |
| Clock Skew: | -0.530 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.148, 59.746%; route: 1.080, 30.040%; tC2Q: 0.367, 10.214% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 5.779 |
| Data Arrival Time | 34.458 |
| Data Required Time | 40.236 |
| From | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0 |
| To | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 |
| Launch Clk | clk[R] |
| Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 30.000 | 0.000 | clk | |||
| 30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 30.683 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
| 30.862 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK |
| 31.230 | 0.367 | tC2Q | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q |
| 31.410 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/I3 |
| 31.662 | 0.252 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.RESET_WAIT_s22/F |
| 31.842 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/I2 |
| 32.285 | 0.443 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s24/F |
| 32.465 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/I2 |
| 32.907 | 0.443 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s20/F |
| 33.087 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I0 |
| 33.592 | 0.505 | tINS | RR | 16 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F |
| 33.772 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/I0 |
| 34.278 | 0.505 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_MODE_CLOSE1_WAIT_s19/F |
| 34.458 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 40.152 | 0.152 | tCL | RR | 3027 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 40.332 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0/CLK |
| 40.297 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 | ||
| 40.236 | -0.061 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/init_state.WRLVL_MODE_CLOSE1_WAIT_s0 |
| Clock Skew: | -0.530 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.148, 59.746%; route: 1.080, 30.040%; tC2Q: 0.367, 10.214% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |