Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\01_gaoyun\gao_project\62_ad7606_ddr3_rgmii\09_01\src\fifo_tx\temp\FIFO\fifo_define.v
H:\01_gaoyun\gao_project\62_ad7606_ddr3_rgmii\09_01\src\fifo_tx\temp\FIFO\fifo_parameter.v
H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\edc.v
H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo.v
H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Fri Sep 01 10:01:06 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_tx
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.45s, Peak memory usage = 39.105MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.105MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.105MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.105MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.105MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.105MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.105MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.105MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.105MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.105MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.105MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.105MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.514s, Peak memory usage = 44.984MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.984MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 44.984MB
Total Time and Memory Usage CPU time = 0h 0m 0.92s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.984MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 54
I/O Buf 54
    IBUF 21
    OBUF 33
Register 97
    DFFPE 5
    DFFCE 92
LUT 125
    LUT2 27
    LUT3 46
    LUT4 52
ALU 33
    ALU 33
SSRAM 3
    RAM16S4 3
INV 5
    INV 5
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 181(130 LUT, 33 ALU, 3 RAM16) / 23040 <1%
Register 97 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 97 / 23685 <1%
BSRAM 1 / 56 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
RdClk Base 10.000 100.0 0.000 5.000 RdClk_ibuf/I
WrClk Base 10.000 100.0 0.000 5.000 WrClk_ibuf/I
fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n4_s2/O
fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n9_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.0(MHz) 103.5(MHz) 8 TOP
2 WrClk 100.0(MHz) 229.5(MHz) 8 TOP
3 fifo_inst/n4_6 100.0(MHz) 1643.7(MHz) 1 TOP
4 fifo_inst/n9_6 100.0(MHz) 1643.7(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.334
Data Arrival Time 10.467
Data Required Time 10.801
From fifo_inst/Small.rq1_wptr_0_s12
To fifo_inst/Rnum_11_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 43 RdClk_ibuf/O
0.863 0.180 tNET RR 3 fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 5.376 tC2Q RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[2]
6.419 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s1/I0
6.924 0.505 tINS RR 1 fifo_inst/Small.wcount_r_1_9_s1/F
7.104 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_7_s0/I2
7.547 0.443 tINS RR 6 fifo_inst/Small.wcount_r_1_7_s0/F
7.727 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s1/I0
8.232 0.505 tINS RR 2 fifo_inst/Small.wcount_r_1_2_s1/F
8.412 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I1
8.907 0.496 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
9.087 0.180 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
9.621 0.534 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
9.621 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
9.669 0.048 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
9.669 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
9.717 0.048 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
9.717 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
9.765 0.048 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
9.765 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
9.813 0.048 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
9.813 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
9.861 0.048 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
9.861 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
9.909 0.048 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
9.909 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
9.957 0.048 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
9.957 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
10.005 0.048 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
10.005 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
10.053 0.048 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
10.053 0.000 tNET RR 1 fifo_inst/rcnt_sub_11_s/CIN
10.287 0.234 tINS RR 1 fifo_inst/rcnt_sub_11_s/SUM
10.467 0.180 tNET RR 1 fifo_inst/Rnum_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 43 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_11_s0/CLK
10.801 -0.061 tSu 1 fifo_inst/Rnum_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.149, 32.784%; route: 1.080, 11.244%; tC2Q: 5.376, 55.972%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 0.382
Data Arrival Time 10.419
Data Required Time 10.801
From fifo_inst/Small.rq1_wptr_0_s12
To fifo_inst/Rnum_10_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 43 RdClk_ibuf/O
0.863 0.180 tNET RR 3 fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 5.376 tC2Q RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[2]
6.419 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s1/I0
6.924 0.505 tINS RR 1 fifo_inst/Small.wcount_r_1_9_s1/F
7.104 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_7_s0/I2
7.547 0.443 tINS RR 6 fifo_inst/Small.wcount_r_1_7_s0/F
7.727 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s1/I0
8.232 0.505 tINS RR 2 fifo_inst/Small.wcount_r_1_2_s1/F
8.412 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I1
8.907 0.496 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
9.087 0.180 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
9.621 0.534 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
9.621 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
9.669 0.048 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
9.669 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
9.717 0.048 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
9.717 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
9.765 0.048 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
9.765 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
9.813 0.048 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
9.813 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
9.861 0.048 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
9.861 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
9.909 0.048 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
9.909 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
9.957 0.048 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
9.957 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
10.005 0.048 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
10.005 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
10.239 0.234 tINS RR 1 fifo_inst/rcnt_sub_10_s/SUM
10.419 0.180 tNET RR 1 fifo_inst/Rnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 43 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_10_s0/CLK
10.801 -0.061 tSu 1 fifo_inst/Rnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.101, 32.446%; route: 1.080, 11.301%; tC2Q: 5.376, 56.253%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 0.430
Data Arrival Time 10.371
Data Required Time 10.801
From fifo_inst/Small.rq1_wptr_0_s12
To fifo_inst/Rnum_9_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 43 RdClk_ibuf/O
0.863 0.180 tNET RR 3 fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 5.376 tC2Q RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[2]
6.419 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s1/I0
6.924 0.505 tINS RR 1 fifo_inst/Small.wcount_r_1_9_s1/F
7.104 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_7_s0/I2
7.547 0.443 tINS RR 6 fifo_inst/Small.wcount_r_1_7_s0/F
7.727 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s1/I0
8.232 0.505 tINS RR 2 fifo_inst/Small.wcount_r_1_2_s1/F
8.412 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I1
8.907 0.496 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
9.087 0.180 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
9.621 0.534 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
9.621 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
9.669 0.048 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
9.669 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
9.717 0.048 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
9.717 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
9.765 0.048 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
9.765 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
9.813 0.048 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
9.813 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
9.861 0.048 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
9.861 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
9.909 0.048 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
9.909 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
9.957 0.048 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
9.957 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
10.191 0.234 tINS RR 1 fifo_inst/rcnt_sub_9_s/SUM
10.371 0.180 tNET RR 1 fifo_inst/Rnum_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 43 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_9_s0/CLK
10.801 -0.061 tSu 1 fifo_inst/Rnum_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.053, 32.105%; route: 1.080, 11.358%; tC2Q: 5.376, 56.537%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 0.478
Data Arrival Time 10.323
Data Required Time 10.801
From fifo_inst/Small.rq1_wptr_0_s12
To fifo_inst/Rnum_8_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 43 RdClk_ibuf/O
0.863 0.180 tNET RR 3 fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 5.376 tC2Q RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[2]
6.419 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s1/I0
6.924 0.505 tINS RR 1 fifo_inst/Small.wcount_r_1_9_s1/F
7.104 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_7_s0/I2
7.547 0.443 tINS RR 6 fifo_inst/Small.wcount_r_1_7_s0/F
7.727 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s1/I0
8.232 0.505 tINS RR 2 fifo_inst/Small.wcount_r_1_2_s1/F
8.412 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I1
8.907 0.496 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
9.087 0.180 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
9.621 0.534 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
9.621 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
9.669 0.048 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
9.669 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
9.717 0.048 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
9.717 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
9.765 0.048 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
9.765 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
9.813 0.048 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
9.813 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
9.861 0.048 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
9.861 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
9.909 0.048 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
9.909 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
10.143 0.234 tINS RR 1 fifo_inst/rcnt_sub_8_s/SUM
10.323 0.180 tNET RR 1 fifo_inst/Rnum_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 43 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_8_s0/CLK
10.801 -0.061 tSu 1 fifo_inst/Rnum_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.005, 31.761%; route: 1.080, 11.416%; tC2Q: 5.376, 56.823%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 0.526
Data Arrival Time 10.275
Data Required Time 10.801
From fifo_inst/Small.rq1_wptr_0_s12
To fifo_inst/Rnum_7_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 43 RdClk_ibuf/O
0.863 0.180 tNET RR 3 fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 5.376 tC2Q RR 4 fifo_inst/Small.rq1_wptr_0_s12/DO[2]
6.419 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s1/I0
6.924 0.505 tINS RR 1 fifo_inst/Small.wcount_r_1_9_s1/F
7.104 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_7_s0/I2
7.547 0.443 tINS RR 6 fifo_inst/Small.wcount_r_1_7_s0/F
7.727 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s1/I0
8.232 0.505 tINS RR 2 fifo_inst/Small.wcount_r_1_2_s1/F
8.412 0.180 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I1
8.907 0.496 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
9.087 0.180 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
9.621 0.534 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
9.621 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
9.669 0.048 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
9.669 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
9.717 0.048 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
9.717 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
9.765 0.048 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
9.765 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
9.813 0.048 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
9.813 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
9.861 0.048 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
9.861 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
10.095 0.234 tINS RR 1 fifo_inst/rcnt_sub_7_s/SUM
10.275 0.180 tNET RR 1 fifo_inst/Rnum_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 43 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Rnum_7_s0/CLK
10.801 -0.061 tSu 1 fifo_inst/Rnum_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.957, 31.413%; route: 1.080, 11.474%; tC2Q: 5.376, 57.113%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%