Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\01_gaoyun\gao_project\53_ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\src\wr_data_fifo\temp\FIFO\fifo_define.v
H:\01_gaoyun\gao_project\53_ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\src\wr_data_fifo\temp\FIFO\fifo_parameter.v
H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\edc.v
H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\fifo.v
H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-2
Part Number GW5A-LV25UG324ES
Device GW5A-25
Created Time Fri Aug 18 10:03:43 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module wr_data_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.462s, Peak memory usage = 39.094MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.094MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.094MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.094MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.094MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.094MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.094MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.094MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.094MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.094MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.094MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.094MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.487s, Peak memory usage = 44.914MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.914MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 44.914MB
Total Time and Memory Usage CPU time = 0h 0m 0.965s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.914MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 176
I/O Buf 176
    IBUF 21
    OBUF 155
Register 95
    DFFPE 6
    DFFCE 89
LUT 110
    LUT2 20
    LUT3 42
    LUT4 48
ALU 30
    ALU 30
SSRAM 3
    RAM16S4 3
INV 4
    INV 4
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 162(114 LUTs, 30 ALUs, 3 SSRAMs) / 23040 <1%
Register 95 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 95 / 23685 <1%
BSRAM 4 / 56 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
RdClk Base 10.000 100.0 0.000 5.000 RdClk_ibuf/I
WrClk Base 10.000 100.0 0.000 5.000 WrClk_ibuf/I
fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n4_s2/O
fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 fifo_inst/n9_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.0(MHz) 137.1(MHz) 10 TOP
2 WrClk 100.0(MHz) 160.8(MHz) 10 TOP
3 fifo_inst/n4_6 100.0(MHz) 1984.1(MHz) 1 TOP
4 fifo_inst/n9_6 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.707
Data Arrival Time 8.120
Data Required Time 10.828
From fifo_inst/Big.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 42 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Big.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 8 fifo_inst/Big.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 2 fifo_inst/Big.rq1_wptr_0_s12/AD[0]
1.849 0.517 tINS FF 3 fifo_inst/Big.rq1_wptr_0_s12/DO[0]
2.086 0.237 tNET FF 1 fifo_inst/Big.wcount_r_7_s0/I1
2.641 0.555 tINS FF 2 fifo_inst/Big.wcount_r_7_s0/F
2.878 0.237 tNET FF 1 fifo_inst/Big.wcount_r_6_s1/I0
3.395 0.517 tINS FF 2 fifo_inst/Big.wcount_r_6_s1/F
3.632 0.237 tNET FF 1 fifo_inst/Big.wcount_r_5_s1/I0
4.148 0.517 tINS FF 6 fifo_inst/Big.wcount_r_5_s1/F
4.385 0.237 tNET FF 1 fifo_inst/Big.wcount_r_0_s0/I0
4.903 0.517 tINS FF 1 fifo_inst/Big.wcount_r_0_s0/F
5.140 0.237 tNET FF 2 fifo_inst/rcnt_sub_0_s/I0
5.689 0.549 tINS FR 1 fifo_inst/rcnt_sub_0_s/COUT
5.689 0.000 tNET RR 2 fifo_inst/rcnt_sub_1_s/CIN
5.724 0.035 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.724 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.759 0.035 tINS FF 1 fifo_inst/rcnt_sub_2_s/COUT
5.759 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.794 0.035 tINS FF 1 fifo_inst/rcnt_sub_3_s/COUT
5.794 0.000 tNET FF 2 fifo_inst/rcnt_sub_4_s/CIN
5.829 0.035 tINS FF 1 fifo_inst/rcnt_sub_4_s/COUT
5.829 0.000 tNET FF 2 fifo_inst/rcnt_sub_5_s/CIN
6.299 0.470 tINS FF 2 fifo_inst/rcnt_sub_5_s/SUM
6.536 0.237 tNET FF 1 fifo_inst/arempty_val_s2/I1
7.091 0.555 tINS FF 1 fifo_inst/arempty_val_s2/F
7.328 0.237 tNET FF 1 fifo_inst/arempty_val_s0/I1
7.883 0.555 tINS FF 1 fifo_inst/arempty_val_s0/F
8.120 0.237 tNET FF 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 42 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.893, 67.414%; route: 2.133, 29.389%; tC2Q: 0.232, 3.197%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 3.781
Data Arrival Time 7.047
Data Required Time 10.828
From fifo_inst/Big.wq2_rptr_7_s0
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.683 0.683 tINS RR 62 WrClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Big.wq2_rptr_7_s0/CLK
1.095 0.232 tC2Q RF 3 fifo_inst/Big.wq2_rptr_7_s0/Q
1.332 0.237 tNET FF 1 fifo_inst/Big.rcount_w_1_9_s1/I1
1.887 0.555 tINS FF 4 fifo_inst/Big.rcount_w_1_9_s1/F
2.124 0.237 tNET FF 1 fifo_inst/Big.rcount_w_1_6_s1/I3
2.495 0.371 tINS FF 4 fifo_inst/Big.rcount_w_1_6_s1/F
2.732 0.237 tNET FF 1 fifo_inst/Big.rcount_w_1_5_s0/I1
3.287 0.555 tINS FF 1 fifo_inst/Big.rcount_w_1_5_s0/F
3.524 0.237 tNET FF 2 fifo_inst/wcnt_sub_5_s/I1
4.094 0.570 tINS FR 1 fifo_inst/wcnt_sub_5_s/COUT
4.094 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
4.129 0.035 tINS RF 1 fifo_inst/wcnt_sub_6_s/COUT
4.129 0.000 tNET FF 2 fifo_inst/wcnt_sub_7_s/CIN
4.164 0.035 tINS FF 1 fifo_inst/wcnt_sub_7_s/COUT
4.164 0.000 tNET FF 2 fifo_inst/wcnt_sub_8_s/CIN
4.199 0.035 tINS FF 1 fifo_inst/wcnt_sub_8_s/COUT
4.199 0.000 tNET FF 2 fifo_inst/wcnt_sub_9_s/CIN
4.234 0.035 tINS FF 1 fifo_inst/wcnt_sub_9_s/COUT
4.234 0.000 tNET FF 2 fifo_inst/wcnt_sub_10_s/CIN
4.270 0.035 tINS FF 1 fifo_inst/wcnt_sub_10_s/COUT
4.270 0.000 tNET FF 2 fifo_inst/wcnt_sub_11_s/CIN
4.740 0.470 tINS FF 2 fifo_inst/wcnt_sub_11_s/SUM
4.977 0.237 tNET FF 1 fifo_inst/awfull_val_s3/I2
5.430 0.453 tINS FF 1 fifo_inst/awfull_val_s3/F
5.667 0.237 tNET FF 1 fifo_inst/awfull_val_s1/I2
6.120 0.453 tINS FF 1 fifo_inst/awfull_val_s1/F
6.357 0.237 tNET FF 1 fifo_inst/awfull_val_s0/I2
6.810 0.453 tINS FF 1 fifo_inst/awfull_val_s0/F
7.047 0.237 tNET FF 1 fifo_inst/Almost_Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.682 0.683 tINS RR 62 WrClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
10.828 -0.035 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.056, 65.588%; route: 1.896, 30.660%; tC2Q: 0.232, 3.752%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 4.064
Data Arrival Time 6.711
Data Required Time 10.776
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 42 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Empty_s0/CLK
1.095 0.232 tC2Q RF 3 fifo_inst/Empty_s0/Q
1.332 0.237 tNET FF 1 fifo_inst/rbin_num_next_0_s5/I0
1.849 0.517 tINS FF 10 fifo_inst/rbin_num_next_0_s5/F
2.086 0.237 tNET FF 1 fifo_inst/rbin_num_next_2_s6/I0
2.602 0.517 tINS FF 5 fifo_inst/rbin_num_next_2_s6/F
2.839 0.237 tNET FF 1 fifo_inst/rbin_num_next_5_s7/I1
3.395 0.555 tINS FF 6 fifo_inst/rbin_num_next_5_s7/F
3.632 0.237 tNET FF 1 fifo_inst/rbin_num_next_6_s5/I1
4.187 0.555 tINS FF 7 fifo_inst/rbin_num_next_6_s5/F
4.424 0.237 tNET FF 1 fifo_inst/Big.rgraynext_6_s0/I0
4.941 0.517 tINS FF 2 fifo_inst/Big.rgraynext_6_s0/F
5.178 0.237 tNET FF 1 fifo_inst/n681_s0/I0
5.727 0.549 tINS FR 1 fifo_inst/n681_s0/COUT
5.727 0.000 tNET RR 1 fifo_inst/n682_s0/CIN
5.762 0.035 tINS RF 1 fifo_inst/n682_s0/COUT
5.762 0.000 tNET FF 1 fifo_inst/n683_s0/CIN
5.797 0.035 tINS FF 1 fifo_inst/n683_s0/COUT
5.797 0.000 tNET FF 1 fifo_inst/n684_s0/CIN
5.832 0.035 tINS FF 2 fifo_inst/n684_s0/COUT
6.069 0.237 tNET FF 1 fifo_inst/n34_s1/I2
6.531 0.462 tINS FR 4 fifo_inst/n34_s1/F
6.711 0.180 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 42 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CLKB
10.776 -0.087 tSu 1 fifo_inst/Big.mem_Big.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.778, 64.590%; route: 1.839, 31.443%; tC2Q: 0.232, 3.967%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 4.064
Data Arrival Time 6.711
Data Required Time 10.776
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_2_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 42 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Empty_s0/CLK
1.095 0.232 tC2Q RF 3 fifo_inst/Empty_s0/Q
1.332 0.237 tNET FF 1 fifo_inst/rbin_num_next_0_s5/I0
1.849 0.517 tINS FF 10 fifo_inst/rbin_num_next_0_s5/F
2.086 0.237 tNET FF 1 fifo_inst/rbin_num_next_2_s6/I0
2.602 0.517 tINS FF 5 fifo_inst/rbin_num_next_2_s6/F
2.839 0.237 tNET FF 1 fifo_inst/rbin_num_next_5_s7/I1
3.395 0.555 tINS FF 6 fifo_inst/rbin_num_next_5_s7/F
3.632 0.237 tNET FF 1 fifo_inst/rbin_num_next_6_s5/I1
4.187 0.555 tINS FF 7 fifo_inst/rbin_num_next_6_s5/F
4.424 0.237 tNET FF 1 fifo_inst/Big.rgraynext_6_s0/I0
4.941 0.517 tINS FF 2 fifo_inst/Big.rgraynext_6_s0/F
5.178 0.237 tNET FF 1 fifo_inst/n681_s0/I0
5.727 0.549 tINS FR 1 fifo_inst/n681_s0/COUT
5.727 0.000 tNET RR 1 fifo_inst/n682_s0/CIN
5.762 0.035 tINS RF 1 fifo_inst/n682_s0/COUT
5.762 0.000 tNET FF 1 fifo_inst/n683_s0/CIN
5.797 0.035 tINS FF 1 fifo_inst/n683_s0/COUT
5.797 0.000 tNET FF 1 fifo_inst/n684_s0/CIN
5.832 0.035 tINS FF 2 fifo_inst/n684_s0/COUT
6.069 0.237 tNET FF 1 fifo_inst/n34_s1/I2
6.531 0.462 tINS FR 4 fifo_inst/n34_s1/F
6.711 0.180 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 42 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CLKB
10.776 -0.087 tSu 1 fifo_inst/Big.mem_Big.mem_0_2_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.778, 64.590%; route: 1.839, 31.443%; tC2Q: 0.232, 3.967%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 4.064
Data Arrival Time 6.711
Data Required Time 10.776
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_1_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.683 0.683 tINS RR 42 RdClk_ibuf/O
0.863 0.180 tNET RR 1 fifo_inst/Empty_s0/CLK
1.095 0.232 tC2Q RF 3 fifo_inst/Empty_s0/Q
1.332 0.237 tNET FF 1 fifo_inst/rbin_num_next_0_s5/I0
1.849 0.517 tINS FF 10 fifo_inst/rbin_num_next_0_s5/F
2.086 0.237 tNET FF 1 fifo_inst/rbin_num_next_2_s6/I0
2.602 0.517 tINS FF 5 fifo_inst/rbin_num_next_2_s6/F
2.839 0.237 tNET FF 1 fifo_inst/rbin_num_next_5_s7/I1
3.395 0.555 tINS FF 6 fifo_inst/rbin_num_next_5_s7/F
3.632 0.237 tNET FF 1 fifo_inst/rbin_num_next_6_s5/I1
4.187 0.555 tINS FF 7 fifo_inst/rbin_num_next_6_s5/F
4.424 0.237 tNET FF 1 fifo_inst/Big.rgraynext_6_s0/I0
4.941 0.517 tINS FF 2 fifo_inst/Big.rgraynext_6_s0/F
5.178 0.237 tNET FF 1 fifo_inst/n681_s0/I0
5.727 0.549 tINS FR 1 fifo_inst/n681_s0/COUT
5.727 0.000 tNET RR 1 fifo_inst/n682_s0/CIN
5.762 0.035 tINS RF 1 fifo_inst/n682_s0/COUT
5.762 0.000 tNET FF 1 fifo_inst/n683_s0/CIN
5.797 0.035 tINS FF 1 fifo_inst/n683_s0/COUT
5.797 0.000 tNET FF 1 fifo_inst/n684_s0/CIN
5.832 0.035 tINS FF 2 fifo_inst/n684_s0/COUT
6.069 0.237 tNET FF 1 fifo_inst/n34_s1/I2
6.531 0.462 tINS FR 4 fifo_inst/n34_s1/F
6.711 0.180 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_1_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.682 0.683 tINS RR 42 RdClk_ibuf/O
10.863 0.180 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_1_s/CLKB
10.776 -0.087 tSu 1 fifo_inst/Big.mem_Big.mem_0_1_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.778, 64.590%; route: 1.839, 31.443%; tC2Q: 0.232, 3.967%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%