--/example_design                              //ʵļ
  -- /bench                                    //_top_tb.vddrģ
     -- ddr_test_top_tb.v                      //HMIC IP Example DesignļΪHMIC IP Example Designļṩʱ
     -- /mem                                   //ddrģ
        -- 2048Mb_mobile_ddr_parameters.vh     //lpddrģ͵ļ
        -- ddr2.v                              //ddr2ģ
        -- ddr2_parameters.vh                  //ddr2ģ͵ļ
        -- ddr3.v                              //ddr3ģ
        -- ddr3_parameters.vh                  //ddr3ģ͵ļ
        -- mobile_ddr.v                        //lpddrģ
  -- /rtl                                      //ʵRTLļHMIC IPĴļ
     -- ipsl_hmic_h_top_test.v                 //HMIC IP Example DesignļHMIC IPΧģ
     -- prbs31_128bit.v                        //prbsģ飬ڲ
     -- test_main_ctrl.v                       //AXIģ飬ڲдָ
     -- test_rd_ctrl_64bit.v                   //AXI 64bitӿڵĶģ飬ƶָͼ
     -- test_rd_ctrl_128bit.v                  //AXI 128bitӿڵĶģ飬ƶָͼ  
     -- test_wr_ctrl_64bit.v                   //AXI 64bitӿڵдģ飬дָͲд
     -- test_wr_ctrl_128bit.v                  //AXI 128bitӿڵдģ飬дָͲд
--/pnr                                         //HMIC IP Example Designۺϲֲ߹
  -- /ctrl_phy_22                              //Logos 22Example Design
     -- ddr_256_left.fdc                       //Logos 22 BG256ʹHMICʱPDSԼļ
     -- ddr_256_right.fdc                      //Logos 22 BG256ʹұHMICʱPDSԼļ
     -- ddr_324_left.fdc                       //Logos 22 BG324ʹHMICʱPDSԼļ
     -- ddr_324_right.fdc                      //Logos 22 BG324ʹұHMICʱPDSԼļ
     -- prj_name.pds                           //HMIC IP Example Design PDSļ
     -- ip_filelist.f                          //HMIC IPfilelist
     -- prj_filelist.f                         //HMIC IP Example Designfilelist
--/rtl                                         //HMIC IPƴ
  -- /pll                                      //PLLģĴ
     -- pll_50_400_v1_1.v                      //HMIC IPPLLģ
  -- ipsl_hmic_h_ddrc_apb_reset_v1_1.v         //APBʼDDRC
  -- ipsl_hmic_h_ddrc_reset_ctrl_v1_1.v        //DDRCλ߼
  -- ipsl_hmic_h_ddrphy_dll_update_ctrl_v1_1.v //DLLupdate߼
  -- ipsl_hmic_h_ddrphy_reset_ctrl_v1_1.v      //DDRPHYĸλ߼
  -- ipsl_hmic_h_ddrphy_training_ctrl_v1_1.v   //DDRPHYtraining߼
  -- ipsl_hmic_h_ddrphy_update_ctrl_v1_1.v     //DDRPHYupdate߼
  -- ipsl_hmic_h_ddrc_top_v1_1.v               //DDRCtop
  -- ipsl_hmic_h_phy_top_v1_1.v                //DDRPHYtop
  -- ipsl_hmic_h_phy_io_v1_1.v                 //DDRPHYIO
--/sim                                         //simulationĿ¼
  -- ctrl_phy_sim.tcl                          //ڷе.tclļ
  -- sim_file_list.f                           //ڷfilelist