FBKCLK; 1
FBKCLK_INT; 0
REFCLK_DIV; 1
FBCLK_DIV; 1
CLKC0_FPHASE; 1
CLKC1_FPHASE; 1
CLKC2_FPHASE; 0
CLKC3_FPHASE; 0
CLKC4_FPHASE; 0
CLKC5_FPHASE; 0
CLKC6_FPHASE; 0
CLKC0_DIV2_ENABLE; 0
CLKC1_DIV2_ENABLE; 0
CLKC2_DIV2_ENABLE; 0
CLKC3_DIV2_ENABLE; 0
CLKC4_DIV2_ENABLE; 0
CLKC5_DIV2_ENABLE; 0
CLKC6_DIV2_ENABLE; 0
PREDIV_MUXC0; 0
PREDIV_MUXC1; 0
PREDIV_MUXC2; 0
PREDIV_MUXC3; 0
PREDIV_MUXC4; 0
PREDIV_MUXC5; 0
PREDIV_MUXC6; 0
CLKC0_CPHASE; 1
CLKC1_CPHASE; 1
CLKC2_CPHASE; 0
CLKC3_CPHASE; 0
CLKC4_CPHASE; 0
CLKC5_CPHASE; 0
CLKC6_CPHASE; 0
CLKC0_DIV; 1
CLKC1_DIV; 1
CLKC2_DIV; 0
CLKC3_DIV; 0
CLKC4_DIV; 0
CLKC5_DIV; 0
CLKC6_DIV; 0
CLKC0_DUTY_INT; 1
CLKC1_DUTY_INT; 1
CLKC2_DUTY_INT; 0
CLKC3_DUTY_INT; 0
CLKC4_DUTY_INT; 0
CLKC5_DUTY_INT; 0
CLKC6_DUTY_INT; 0
FREQ_OFFSET; 0
DIVOUT_MUXC0; 0
DIVOUT_MUXC1; 0
DIVOUT_MUXC2; 0
DIVOUT_MUXC3; 0
DIVOUT_MUXC4; 0
DIVOUT_MUXC5; 0
DIVOUT_MUXC6; 0
MAIN_MUXC; 0
CLKC0_ENABLE; 1
CLKC1_ENABLE; 1
CLKC2_ENABLE; 0
CLKC3_ENABLE; 0
CLKC4_ENABLE; 0
CLKC5_ENABLE; 0
CLKC6_ENABLE; 0
CLK_MAIN_ENABLE; 0
WORK_MODE; 0
FIN; 1
FEEDBK_MODE; 1
PD_DIG; 0
REFCLK_USR_RST; 0
PLL_USR_RST; 1
PLL_FEED_TYPE; 1
LPF_RES; 1
LPF_CAP; 1
ICP_CUR; 1
GMC_GAIN; 1
FRAC_ENABLE; 1
DITHER_ENABLE; 1
SDM_FRAC; 1
SSC_AMP; 1
MPHASE_ENABLE; 1
PHASE_PATH_SEL; 0
DYN_PHASE_PATH_SEL; 1
DYN_FPHASE_EN; 1
CLKC0_FPHASE_RSTSEL; 1
CLKC1_FPHASE_RSTSEL; 1
CLKC2_FPHASE_RSTSEL; 0
CLKC3_FPHASE_RSTSEL; 0
CLKC4_FPHASE_RSTSEL; 0
CLKC5_FPHASE_RSTSEL; 0
CLKC6_FPHASE_RSTSEL; 0
DYN_CPHASE_CLKC0_DIV2_EN; 0
DYN_CPHASE_CLKC1_DIV2_EN; 0
DYN_CPHASE_CLKC2_DIV2_EN; 0
DYN_CPHASE_CLKC3_DIV2_EN; 0
DYN_CPHASE_CLKC4_DIV2_EN; 0
DYN_CPHASE_CLKC5_DIV2_EN; 0
DYN_CPHASE_CLKC6_DIV2_EN; 0
DYN_CPHASE_CLKC0_DIV_EN; 0
DYN_CPHASE_CLKC1_DIV_EN; 0
DYN_CPHASE_CLKC2_DIV_EN; 0
DYN_CPHASE_CLKC3_DIV_EN; 0
DYN_CPHASE_CLKC4_DIV_EN; 0
DYN_CPHASE_CLKC5_DIV_EN; 0
DYN_CPHASE_CLKC6_DIV_EN; 0
CLKC0_CPHASE_DIV2; 0
CLKC1_CPHASE_DIV2; 0
CLKC2_CPHASE_DIV2; 0
CLKC3_CPHASE_DIV2; 0
CLKC4_CPHASE_DIV2; 0
CLKC5_CPHASE_DIV2; 0
CLKC6_CPHASE_DIV2; 0
CLKC0_DUTY50; 1
CLKC1_DUTY50; 1
CLKC2_DUTY50; 0
CLKC3_DUTY50; 0
CLKC4_DUTY50; 0
CLKC5_DUTY50; 0
CLKC6_DUTY50; 0
CLKC0_USR_RST; 0
CLKC1_USR_RST; 0
INTPI; 1
SSC_ENABLE; 1
SSC_MODE; 1
EXT_USR_FREQ_EN; 0
SSC_FREQ_DIV; 1
SSC_RNGE; 1
HIGH_SPEED_EN; 1
REFCLK_OUT_ENABLE; 0
REFCLK_DET_BYP; 0
DERIVE_PLL_CLOCKS; 0
GEN_BASIC_CLOCK; 0