Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\ad7606_driver.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\AD7606_UART.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\adc_write_ctrl.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\cmd_ctrl.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\uart_byte_rx.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\uart_byte_tx.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\uart_cmd.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\uart_send_ctrl.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\fifo_generator_0\fifo_generator_0.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Fri Jun 27 10:45:44 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AD7606_UART
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 304.898MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 304.898MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 304.898MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 304.898MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 304.898MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 304.898MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 304.898MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 304.898MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 304.898MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 304.898MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 304.898MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.892s, Peak memory usage = 312.043MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 312.465MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 312.465MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 312.465MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 28
I/O Buf 28
    IBUF 20
    OBUF 8
Register 474
    DFFRE 194
    DFFPE 21
    DFFCE 259
LUT 472
    LUT2 89
    LUT3 125
    LUT4 258
ALU 70
    ALU 70
INV 1
    INV 1
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 543(473 LUT, 70 ALU) / 23040 3%
Register 474 / 23685 3%
  --Register as Latch 0 / 23685 0%
  --Register as FF 474 / 23685 3%
BSRAM 16 / 56 29%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 Clk Base 10.000 100.000 0.000 5.000 Clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 Clk 100.000(MHz) 167.560(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.032
Data Arrival Time 6.217
Data Required Time 10.249
From your_instance_name/fifo_inst/Empty_s0
To your_instance_name/fifo_inst/Empty_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 506 Clk_ibuf/O
0.300 0.300 tNET RR 1 your_instance_name/fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 6 your_instance_name/fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 your_instance_name/fifo_inst/n29_s0/I0
1.327 0.421 tINS RR 18 your_instance_name/fifo_inst/n29_s0/F
1.627 0.300 tNET RR 1 your_instance_name/fifo_inst/rbin_num_next_3_s4/I0
2.048 0.421 tINS RR 7 your_instance_name/fifo_inst/rbin_num_next_3_s4/F
2.348 0.300 tNET RR 1 your_instance_name/fifo_inst/rbin_num_next_6_s4/I0
2.769 0.421 tINS RR 8 your_instance_name/fifo_inst/rbin_num_next_6_s4/F
3.069 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.rgraynext_7_s1/I0
3.490 0.421 tINS RR 2 your_instance_name/fifo_inst/Equal.rgraynext_7_s1/F
3.790 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.rgraynext_7_s0/I0
4.211 0.421 tINS RR 2 your_instance_name/fifo_inst/Equal.rgraynext_7_s0/F
4.511 0.300 tNET RR 2 your_instance_name/fifo_inst/n148_s0/I0
4.956 0.445 tINS RF 1 your_instance_name/fifo_inst/n148_s0/COUT
4.956 0.000 tNET FF 2 your_instance_name/fifo_inst/n149_s0/CIN
4.996 0.040 tINS FR 1 your_instance_name/fifo_inst/n149_s0/COUT
4.996 0.000 tNET RR 2 your_instance_name/fifo_inst/n150_s0/CIN
5.036 0.040 tINS RR 1 your_instance_name/fifo_inst/n150_s0/COUT
5.036 0.000 tNET RR 2 your_instance_name/fifo_inst/n151_s0/CIN
5.076 0.040 tINS RR 1 your_instance_name/fifo_inst/n151_s0/COUT
5.076 0.000 tNET RR 2 your_instance_name/fifo_inst/n152_s0/CIN
5.116 0.040 tINS RR 1 your_instance_name/fifo_inst/n152_s0/COUT
5.116 0.000 tNET RR 2 your_instance_name/fifo_inst/n153_s0/CIN
5.156 0.040 tINS RR 1 your_instance_name/fifo_inst/n153_s0/COUT
5.156 0.000 tNET RR 2 your_instance_name/fifo_inst/n154_s0/CIN
5.196 0.040 tINS RR 1 your_instance_name/fifo_inst/n154_s0/COUT
5.496 0.300 tNET RR 1 your_instance_name/fifo_inst/rempty_val_s1/I0
5.917 0.421 tINS RR 1 your_instance_name/fifo_inst/rempty_val_s1/F
6.217 0.300 tNET RR 1 your_instance_name/fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 506 Clk_ibuf/O
10.300 0.300 tNET RR 1 your_instance_name/fifo_inst/Empty_s0/CLK
10.249 -0.051 tSu 1 your_instance_name/fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 3.211, 54.267%; route: 2.400, 40.561%; tC2Q: 0.306, 5.172%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 5.289
Data Arrival Time 4.960
Data Required Time 10.249
From cmd_ctrl/DataNum_0_s0
To adc_write_ctrl/sample_en_s5
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 506 Clk_ibuf/O
0.300 0.300 tNET RR 1 cmd_ctrl/DataNum_0_s0/CLK
0.606 0.306 tC2Q RR 1 cmd_ctrl/DataNum_0_s0/Q
0.906 0.300 tNET RR 2 adc_write_ctrl/n62_s/I0
1.491 0.585 tINS RR 1 adc_write_ctrl/n62_s/SUM
1.791 0.300 tNET RR 1 adc_write_ctrl/n63_s44/I1
2.204 0.413 tINS RR 1 adc_write_ctrl/n63_s44/F
2.504 0.300 tNET RR 2 adc_write_ctrl/n63_s31/I0
2.949 0.445 tINS RF 1 adc_write_ctrl/n63_s31/COUT
2.949 0.000 tNET FF 2 adc_write_ctrl/n63_s32/CIN
2.989 0.040 tINS FR 1 adc_write_ctrl/n63_s32/COUT
2.989 0.000 tNET RR 2 adc_write_ctrl/n63_s33/CIN
3.029 0.040 tINS RR 1 adc_write_ctrl/n63_s33/COUT
3.029 0.000 tNET RR 2 adc_write_ctrl/n63_s34/CIN
3.069 0.040 tINS RR 1 adc_write_ctrl/n63_s34/COUT
3.069 0.000 tNET RR 2 adc_write_ctrl/n63_s35/CIN
3.109 0.040 tINS RR 1 adc_write_ctrl/n63_s35/COUT
3.109 0.000 tNET RR 2 adc_write_ctrl/n63_s36/CIN
3.149 0.040 tINS RR 1 adc_write_ctrl/n63_s36/COUT
3.149 0.000 tNET RR 2 adc_write_ctrl/n63_s37/CIN
3.189 0.040 tINS RR 1 adc_write_ctrl/n63_s37/COUT
3.189 0.000 tNET RR 2 adc_write_ctrl/n63_s38/CIN
3.229 0.040 tINS RR 1 adc_write_ctrl/n63_s38/COUT
3.229 0.000 tNET RR 2 adc_write_ctrl/n63_s39/CIN
3.269 0.040 tINS RR 1 adc_write_ctrl/n63_s39/COUT
3.269 0.000 tNET RR 2 adc_write_ctrl/n63_s40/CIN
3.309 0.040 tINS RR 1 adc_write_ctrl/n63_s40/COUT
3.309 0.000 tNET RR 2 adc_write_ctrl/n63_s41/CIN
3.349 0.040 tINS RR 1 adc_write_ctrl/n63_s41/COUT
3.349 0.000 tNET RR 2 adc_write_ctrl/n63_s42/CIN
3.389 0.040 tINS RR 1 adc_write_ctrl/n63_s42/COUT
3.389 0.000 tNET RR 2 adc_write_ctrl/n63_s43/CIN
3.429 0.040 tINS RR 2 adc_write_ctrl/n63_s43/COUT
3.729 0.300 tNET RR 1 adc_write_ctrl/sample_en_reg_s4/I0
4.150 0.421 tINS RR 1 adc_write_ctrl/sample_en_reg_s4/F
4.450 0.300 tNET RR 1 adc_write_ctrl/n70_s2/I3
4.660 0.210 tINS RR 1 adc_write_ctrl/n70_s2/F
4.960 0.300 tNET RR 1 adc_write_ctrl/sample_en_s5/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 506 Clk_ibuf/O
10.300 0.300 tNET RR 1 adc_write_ctrl/sample_en_s5/CLK
10.249 -0.051 tSu 1 adc_write_ctrl/sample_en_s5
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.554, 54.806%; route: 1.800, 38.627%; tC2Q: 0.306, 6.567%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 5.609
Data Arrival Time 4.442
Data Required Time 10.051
From cmd_ctrl/DataNum_0_s0
To adc_write_ctrl/sample_en_reg_s1
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 506 Clk_ibuf/O
0.300 0.300 tNET RR 1 cmd_ctrl/DataNum_0_s0/CLK
0.606 0.306 tC2Q RR 1 cmd_ctrl/DataNum_0_s0/Q
0.906 0.300 tNET RR 2 adc_write_ctrl/n62_s/I0
1.491 0.585 tINS RR 1 adc_write_ctrl/n62_s/SUM
1.791 0.300 tNET RR 1 adc_write_ctrl/n63_s44/I1
2.204 0.413 tINS RR 1 adc_write_ctrl/n63_s44/F
2.504 0.300 tNET RR 2 adc_write_ctrl/n63_s31/I0
2.949 0.445 tINS RF 1 adc_write_ctrl/n63_s31/COUT
2.949 0.000 tNET FF 2 adc_write_ctrl/n63_s32/CIN
2.989 0.040 tINS FR 1 adc_write_ctrl/n63_s32/COUT
2.989 0.000 tNET RR 2 adc_write_ctrl/n63_s33/CIN
3.029 0.040 tINS RR 1 adc_write_ctrl/n63_s33/COUT
3.029 0.000 tNET RR 2 adc_write_ctrl/n63_s34/CIN
3.069 0.040 tINS RR 1 adc_write_ctrl/n63_s34/COUT
3.069 0.000 tNET RR 2 adc_write_ctrl/n63_s35/CIN
3.109 0.040 tINS RR 1 adc_write_ctrl/n63_s35/COUT
3.109 0.000 tNET RR 2 adc_write_ctrl/n63_s36/CIN
3.149 0.040 tINS RR 1 adc_write_ctrl/n63_s36/COUT
3.149 0.000 tNET RR 2 adc_write_ctrl/n63_s37/CIN
3.189 0.040 tINS RR 1 adc_write_ctrl/n63_s37/COUT
3.189 0.000 tNET RR 2 adc_write_ctrl/n63_s38/CIN
3.229 0.040 tINS RR 1 adc_write_ctrl/n63_s38/COUT
3.229 0.000 tNET RR 2 adc_write_ctrl/n63_s39/CIN
3.269 0.040 tINS RR 1 adc_write_ctrl/n63_s39/COUT
3.269 0.000 tNET RR 2 adc_write_ctrl/n63_s40/CIN
3.309 0.040 tINS RR 1 adc_write_ctrl/n63_s40/COUT
3.309 0.000 tNET RR 2 adc_write_ctrl/n63_s41/CIN
3.349 0.040 tINS RR 1 adc_write_ctrl/n63_s41/COUT
3.349 0.000 tNET RR 2 adc_write_ctrl/n63_s42/CIN
3.389 0.040 tINS RR 1 adc_write_ctrl/n63_s42/COUT
3.389 0.000 tNET RR 2 adc_write_ctrl/n63_s43/CIN
3.429 0.040 tINS RR 2 adc_write_ctrl/n63_s43/COUT
3.729 0.300 tNET RR 1 adc_write_ctrl/sample_en_reg_s5/I1
4.142 0.413 tINS RR 1 adc_write_ctrl/sample_en_reg_s5/F
4.442 0.300 tNET RR 1 adc_write_ctrl/sample_en_reg_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 506 Clk_ibuf/O
10.300 0.300 tNET RR 1 adc_write_ctrl/sample_en_reg_s1/CLK
10.051 -0.249 tSu 1 adc_write_ctrl/sample_en_reg_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.336, 56.398%; route: 1.500, 36.214%; tC2Q: 0.306, 7.388%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 5.738
Data Arrival Time 4.511
Data Required Time 10.249
From your_instance_name/fifo_inst/Full_s0
To your_instance_name/fifo_inst/Full_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 506 Clk_ibuf/O
0.300 0.300 tNET RR 1 your_instance_name/fifo_inst/Full_s0/CLK
0.606 0.306 tC2Q RR 5 your_instance_name/fifo_inst/Full_s0/Q
0.906 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.wgraynext_2_s1/I0
1.327 0.421 tINS RR 22 your_instance_name/fifo_inst/Equal.wgraynext_2_s1/F
1.627 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.wgraynext_6_s1/I0
2.048 0.421 tINS RR 3 your_instance_name/fifo_inst/Equal.wgraynext_6_s1/F
2.348 0.300 tNET RR 1 your_instance_name/fifo_inst/wfull_val_s5/I0
2.769 0.421 tINS RR 1 your_instance_name/fifo_inst/wfull_val_s5/F
3.069 0.300 tNET RR 1 your_instance_name/fifo_inst/wfull_val_s1/I0
3.490 0.421 tINS RR 1 your_instance_name/fifo_inst/wfull_val_s1/F
3.790 0.300 tNET RR 1 your_instance_name/fifo_inst/wfull_val_s0/I0
4.211 0.421 tINS RR 1 your_instance_name/fifo_inst/wfull_val_s0/F
4.511 0.300 tNET RR 1 your_instance_name/fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 506 Clk_ibuf/O
10.300 0.300 tNET RR 1 your_instance_name/fifo_inst/Full_s0/CLK
10.249 -0.051 tSu 1 your_instance_name/fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.105, 49.988%; route: 1.800, 42.745%; tC2Q: 0.306, 7.267%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 5.738
Data Arrival Time 4.511
Data Required Time 10.249
From your_instance_name/fifo_inst/Empty_s0
To your_instance_name/fifo_inst/Equal.rptr_7_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 506 Clk_ibuf/O
0.300 0.300 tNET RR 1 your_instance_name/fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 6 your_instance_name/fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 your_instance_name/fifo_inst/n29_s0/I0
1.327 0.421 tINS RR 18 your_instance_name/fifo_inst/n29_s0/F
1.627 0.300 tNET RR 1 your_instance_name/fifo_inst/rbin_num_next_3_s4/I0
2.048 0.421 tINS RR 7 your_instance_name/fifo_inst/rbin_num_next_3_s4/F
2.348 0.300 tNET RR 1 your_instance_name/fifo_inst/rbin_num_next_6_s4/I0
2.769 0.421 tINS RR 8 your_instance_name/fifo_inst/rbin_num_next_6_s4/F
3.069 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.rgraynext_7_s1/I0
3.490 0.421 tINS RR 2 your_instance_name/fifo_inst/Equal.rgraynext_7_s1/F
3.790 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.rgraynext_7_s0/I0
4.211 0.421 tINS RR 2 your_instance_name/fifo_inst/Equal.rgraynext_7_s0/F
4.511 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.rptr_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 506 Clk_ibuf/O
10.300 0.300 tNET RR 1 your_instance_name/fifo_inst/Equal.rptr_7_s0/CLK
10.249 -0.051 tSu 1 your_instance_name/fifo_inst/Equal.rptr_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.105, 49.988%; route: 1.800, 42.745%; tC2Q: 0.306, 7.267%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%