Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\fifo_generator_0\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\fifo_generator_0\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Fri Jun 27 10:42:06 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_generator_0
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.388s, Peak memory usage = 94.988MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.988MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 94.988MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.988MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 94.988MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 94.988MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.988MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.988MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 94.988MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 94.988MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.988MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.988MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.426s, Peak memory usage = 109.684MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 109.973MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 109.973MB
Total Time and Memory Usage CPU time = 0h 0m 0.717s, Elapsed time = 0h 0m 0.929s, Peak memory usage = 109.973MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 38
I/O Buf 38
    IBUF 20
    OBUF 18
Register 120
    DFFRE 120
LUT 107
    LUT2 28
    LUT3 29
    LUT4 50
ALU 14
    ALU 14
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 121(107 LUT, 14 ALU) / 23040 <1%
Register 120 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 120 / 23685 <1%
BSRAM 16 / 56 29%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 167.560(MHz) 10 TOP
2 WrClk 100.000(MHz) 234.632(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.032
Data Arrival Time 6.217
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 76 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/n29_s0/I0
1.327 0.421 tINS RR 18 fifo_inst/n29_s0/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I0
2.048 0.421 tINS RR 7 fifo_inst/rbin_num_next_3_s4/F
2.348 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I0
2.769 0.421 tINS RR 8 fifo_inst/rbin_num_next_6_s4/F
3.069 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_7_s1/I0
3.490 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_7_s1/F
3.790 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_7_s0/I0
4.211 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_7_s0/F
4.511 0.300 tNET RR 2 fifo_inst/n148_s0/I0
4.956 0.445 tINS RF 1 fifo_inst/n148_s0/COUT
4.956 0.000 tNET FF 2 fifo_inst/n149_s0/CIN
4.996 0.040 tINS FR 1 fifo_inst/n149_s0/COUT
4.996 0.000 tNET RR 2 fifo_inst/n150_s0/CIN
5.036 0.040 tINS RR 1 fifo_inst/n150_s0/COUT
5.036 0.000 tNET RR 2 fifo_inst/n151_s0/CIN
5.076 0.040 tINS RR 1 fifo_inst/n151_s0/COUT
5.076 0.000 tNET RR 2 fifo_inst/n152_s0/CIN
5.116 0.040 tINS RR 1 fifo_inst/n152_s0/COUT
5.116 0.000 tNET RR 2 fifo_inst/n153_s0/CIN
5.156 0.040 tINS RR 1 fifo_inst/n153_s0/COUT
5.156 0.000 tNET RR 2 fifo_inst/n154_s0/CIN
5.196 0.040 tINS RR 1 fifo_inst/n154_s0/COUT
5.496 0.300 tNET RR 1 fifo_inst/rempty_val_s1/I0
5.917 0.421 tINS RR 1 fifo_inst/rempty_val_s1/F
6.217 0.300 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 76 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 3.211, 54.267%; route: 2.400, 40.561%; tC2Q: 0.306, 5.172%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 5.738
Data Arrival Time 4.511
Data Required Time 10.249
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 76 WrClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Full_s0/CLK
0.606 0.306 tC2Q RR 6 fifo_inst/Full_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.327 0.421 tINS RR 22 fifo_inst/Equal.wgraynext_2_s1/F
1.627 0.300 tNET RR 1 fifo_inst/Equal.wgraynext_6_s1/I0
2.048 0.421 tINS RR 3 fifo_inst/Equal.wgraynext_6_s1/F
2.348 0.300 tNET RR 1 fifo_inst/wfull_val_s5/I0
2.769 0.421 tINS RR 1 fifo_inst/wfull_val_s5/F
3.069 0.300 tNET RR 1 fifo_inst/wfull_val_s1/I0
3.490 0.421 tINS RR 1 fifo_inst/wfull_val_s1/F
3.790 0.300 tNET RR 1 fifo_inst/wfull_val_s0/I0
4.211 0.421 tINS RR 1 fifo_inst/wfull_val_s0/F
4.511 0.300 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 76 WrClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Full_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.105, 49.988%; route: 1.800, 42.745%; tC2Q: 0.306, 7.267%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 5.738
Data Arrival Time 4.511
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_7_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 76 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/n29_s0/I0
1.327 0.421 tINS RR 18 fifo_inst/n29_s0/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I0
2.048 0.421 tINS RR 7 fifo_inst/rbin_num_next_3_s4/F
2.348 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I0
2.769 0.421 tINS RR 8 fifo_inst/rbin_num_next_6_s4/F
3.069 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_7_s1/I0
3.490 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_7_s1/F
3.790 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_7_s0/I0
4.211 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_7_s0/F
4.511 0.300 tNET RR 1 fifo_inst/Equal.rptr_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 76 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Equal.rptr_7_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Equal.rptr_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.105, 49.988%; route: 1.800, 42.745%; tC2Q: 0.306, 7.267%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 5.738
Data Arrival Time 4.511
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_8_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 76 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/n29_s0/I0
1.327 0.421 tINS RR 18 fifo_inst/n29_s0/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I0
2.048 0.421 tINS RR 7 fifo_inst/rbin_num_next_3_s4/F
2.348 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I0
2.769 0.421 tINS RR 8 fifo_inst/rbin_num_next_6_s4/F
3.069 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_7_s1/I0
3.490 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_7_s1/F
3.790 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_8_s0/I0
4.211 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_8_s0/F
4.511 0.300 tNET RR 1 fifo_inst/Equal.rptr_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 76 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Equal.rptr_8_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Equal.rptr_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.105, 49.988%; route: 1.800, 42.745%; tC2Q: 0.306, 7.267%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 5.738
Data Arrival Time 4.511
Data Required Time 10.249
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_9_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 76 RdClk_ibuf/O
0.300 0.300 tNET RR 1 fifo_inst/Empty_s0/CLK
0.606 0.306 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.906 0.300 tNET RR 1 fifo_inst/n29_s0/I0
1.327 0.421 tINS RR 18 fifo_inst/n29_s0/F
1.627 0.300 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I0
2.048 0.421 tINS RR 7 fifo_inst/rbin_num_next_3_s4/F
2.348 0.300 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I0
2.769 0.421 tINS RR 8 fifo_inst/rbin_num_next_6_s4/F
3.069 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_9_s3/I0
3.490 0.421 tINS RR 6 fifo_inst/Equal.rgraynext_9_s3/F
3.790 0.300 tNET RR 1 fifo_inst/Equal.rgraynext_9_s0/I0
4.211 0.421 tINS RR 2 fifo_inst/Equal.rgraynext_9_s0/F
4.511 0.300 tNET RR 1 fifo_inst/Equal.rptr_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 76 RdClk_ibuf/O
10.300 0.300 tNET RR 1 fifo_inst/Equal.rptr_9_s0/CLK
10.249 -0.051 tSu 1 fifo_inst/Equal.rptr_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 2.105, 49.988%; route: 1.800, 42.745%; tC2Q: 0.306, 7.267%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%