Timing Messages

Report Title	Timing Analysis Report
Design File	C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\impl\gwsynthesis\ad7606_fifo_uart.vg
Physical Constraints File	C:\Users\24165\Desktop\6_27\ad7606_fifo_uart\src\ad7606_fifo_uart.cst
Timing Constraint File	---
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW5A-LV25UG324C2/I1
Device	GW5A-25
Device Version	A
Created Time	Fri Jun 27 11:05:08 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	1581
Numbers of Endpoints Analyzed	2054
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	Clk	Base	10.000	100.000	0.000	5.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	100.000(MHz)	190.476(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
Clk	Setup	0.000	0
Clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.750	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_5_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.006	5.007
2	4.895	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_6_s0/CE	Clk:[R]	Clk:[R]	10.000	0.002	4.855
3	5.104	your_instance_name/fifo_inst/Empty_s0/Q	your_instance_name/fifo_inst/Empty_s0/D	Clk:[R]	Clk:[R]	10.000	0.000	4.845
4	5.140	your_instance_name/fifo_inst/Equal.wbin_1_s0/Q	your_instance_name/fifo_inst/Full_s0/D	Clk:[R]	Clk:[R]	10.000	-0.016	4.826
5	5.201	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_9_s0/CE	Clk:[R]	Clk:[R]	10.000	0.002	4.549
6	5.332	your_instance_name/fifo_inst/Equal.wbin_1_s0/Q	your_instance_name/fifo_inst/Equal.wptr_9_s0/D	Clk:[R]	Clk:[R]	10.000	0.025	4.592
7	5.514	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_3_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.006	4.243
8	5.706	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_4_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.013	4.059
9	5.735	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_2_s0/CE	Clk:[R]	Clk:[R]	10.000	0.002	4.015
10	5.742	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_1_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.006	4.015
11	5.796	ad7606_driver/cnt_2_s0/Q	ad7606_driver/Conv_s2/CE	Clk:[R]	Clk:[R]	10.000	-0.001	3.957
12	5.880	your_instance_name/fifo_inst/Equal.wbin_1_s0/Q	your_instance_name/fifo_inst/Equal.wbin_9_s0/D	Clk:[R]	Clk:[R]	10.000	0.000	4.069
13	5.963	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/cmdvalid_s1/CE	Clk:[R]	Clk:[R]	10.000	-0.041	3.829
14	5.971	ad7606_driver/cnt_2_s0/Q	ad7606_driver/ad7606_convst_o_s1/D	Clk:[R]	Clk:[R]	10.000	-0.006	3.989
15	6.002	ad7606_driver/cnt_2_s0/Q	ad7606_driver/state_0_s1/D	Clk:[R]	Clk:[R]	10.000	-0.001	3.949
16	6.041	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_11_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.024	3.734
17	6.043	ad7606_driver/state_2_s0/Q	ad7606_driver/data_mult_ch_12_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.026	3.734
18	6.047	uart_byte_tx/r_data_byte_3_s0/Q	uart_byte_tx/Rs232_Tx_s0/D	Clk:[R]	Clk:[R]	10.000	0.027	3.875
19	6.065	ad7606_driver/cnt_2_s0/Q	ad7606_driver/state_2_s0/D	Clk:[R]	Clk:[R]	10.000	0.000	3.884
20	6.088	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/data_2_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.028	3.691
21	6.092	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/data_20_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.032	3.691
22	6.092	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/data_15_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.032	3.691
23	6.092	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/data_14_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.032	3.691
24	6.092	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/data_9_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.032	3.691
25	6.092	uart_cmd/data_str[7]_3_s0/Q	uart_cmd/data_7_s0/CE	Clk:[R]	Clk:[R]	10.000	-0.032	3.691

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.193	adc_write_ctrl/fifowrdata_8_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s/DI[0]	Clk:[R]	Clk:[R]	0.000	-0.005	0.235
2	0.193	adc_write_ctrl/fifowrdata_4_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_4_s/DI[0]	Clk:[R]	Clk:[R]	0.000	-0.005	0.235
3	0.193	adc_write_ctrl/fifowrdata_2_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[0]	Clk:[R]	Clk:[R]	0.000	-0.005	0.235
4	0.193	adc_write_ctrl/fifowrdata_0_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[0]	Clk:[R]	Clk:[R]	0.000	-0.005	0.235
5	0.193	adc_write_ctrl/fifowrdata_13_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/DI[0]	Clk:[R]	Clk:[R]	0.000	-0.005	0.235
6	0.193	adc_write_ctrl/fifowrdata_6_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s/DI[0]	Clk:[R]	Clk:[R]	0.000	-0.005	0.235
7	0.228	your_instance_name/fifo_inst/rbin_num_10_s0/Q	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s/ADB[10]	Clk:[R]	Clk:[R]	0.000	0.020	0.243
8	0.275	uart_byte_rx/r_data[0]_0_s0/Q	uart_byte_rx/r_data[0]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
9	0.275	uart_byte_rx/r_data[0]_1_s0/Q	uart_byte_rx/r_data[0]_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
10	0.275	uart_byte_rx/r_data[5]_1_s0/Q	uart_byte_rx/r_data[5]_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
11	0.275	uart_byte_rx/r_data[5]_2_s0/Q	uart_byte_rx/r_data[5]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
12	0.275	uart_byte_rx/div_cnt_2_s0/Q	uart_byte_rx/div_cnt_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
13	0.275	uart_byte_tx/div_cnt_3_s0/Q	uart_byte_tx/div_cnt_3_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
14	0.275	uart_byte_tx/div_cnt_14_s0/Q	uart_byte_tx/div_cnt_14_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
15	0.275	adc_write_ctrl/skip_cnt_1_s1/Q	adc_write_ctrl/skip_cnt_1_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
16	0.275	adc_write_ctrl/skip_cnt_3_s1/Q	adc_write_ctrl/skip_cnt_3_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.300
17	0.278	uart_byte_rx/r_data[2]_0_s0/Q	uart_byte_rx/r_data[2]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
18	0.278	uart_byte_rx/div_cnt_0_s0/Q	uart_byte_rx/div_cnt_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
19	0.278	uart_byte_rx/div_cnt_4_s0/Q	uart_byte_rx/div_cnt_4_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
20	0.278	uart_byte_tx/bps_cnt_3_s1/Q	uart_byte_tx/bps_cnt_3_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
21	0.278	uart_byte_tx/div_cnt_11_s0/Q	uart_byte_tx/div_cnt_11_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
22	0.278	adc_write_ctrl/data_cnt_12_s1/Q	adc_write_ctrl/data_cnt_12_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
23	0.278	your_instance_name/fifo_inst/Equal.wbin_7_s0/Q	your_instance_name/fifo_inst/Equal.wbin_7_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
24	0.278	your_instance_name/fifo_inst/Equal.wbin_8_s0/Q	your_instance_name/fifo_inst/Equal.wbin_8_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303
25	0.278	your_instance_name/fifo_inst/Equal.wbin_11_s0/Q	your_instance_name/fifo_inst/Equal.wbin_11_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s
2	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_5_s
3	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s
4	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s
5	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_14_s
6	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s
7	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s
8	3.279	4.141	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s
9	3.282	4.144	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s
10	3.282	4.144	0.862	Low Pulse Width	Clk	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.750
Data Arrival Time	7.134
Data Required Time	11.884
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_5_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
7.134	2.954	tNET	RR	1	IOB91[B]	ad7606_driver/data_mult_ch_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.133	1.546	tNET	RR	1	IOB91[B]	ad7606_driver/data_mult_ch_5_s0/CLK
11.884	-0.249	tSu		1	IOB91[B]	ad7606_driver/data_mult_ch_5_s0

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 20.691%; route: 3.677, 73.437%; tC2Q: 0.294, 5.872%
Required Clock Path Delay	cell: 0.587, 27.512%; route: 1.546, 72.488%

Path2

Path Summary:

Slack	4.895
Data Arrival Time	6.982
Data Required Time	11.877
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
6.982	2.802	tNET	RR	1	IOB91[A]	ad7606_driver/data_mult_ch_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.126	1.539	tNET	RR	1	IOB91[A]	ad7606_driver/data_mult_ch_6_s0/CLK
11.877	-0.249	tSu		1	IOB91[A]	ad7606_driver/data_mult_ch_6_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 21.339%; route: 3.525, 72.606%; tC2Q: 0.294, 6.056%
Required Clock Path Delay	cell: 0.587, 27.609%; route: 1.539, 72.391%

Path3

Path Summary:

Slack	5.104
Data Arrival Time	6.993
Data Required Time	12.097
From	your_instance_name/fifo_inst/Empty_s0
To	your_instance_name/fifo_inst/Empty_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.148	1.561	tNET	RR	1	R22C47[0][B]	your_instance_name/fifo_inst/Empty_s0/CLK
2.454	0.306	tC2Q	RR	6	R22C47[0][B]	your_instance_name/fifo_inst/Empty_s0/Q
3.063	0.609	tNET	RR	1	R20C42[3][B]	your_instance_name/fifo_inst/n29_s0/I0
3.461	0.398	tINS	RR	18	R20C42[3][B]	your_instance_name/fifo_inst/n29_s0/F
3.621	0.160	tNET	RR	1	R20C44[3][B]	your_instance_name/fifo_inst/rbin_num_next_3_s4/I0
4.019	0.398	tINS	RR	7	R20C44[3][B]	your_instance_name/fifo_inst/rbin_num_next_3_s4/F
4.151	0.132	tNET	RR	1	R20C45[3][A]	your_instance_name/fifo_inst/rbin_num_next_6_s4/I0
4.383	0.232	tINS	RF	8	R20C45[3][A]	your_instance_name/fifo_inst/rbin_num_next_6_s4/F
4.517	0.134	tNET	FF	1	R21C45[2][B]	your_instance_name/fifo_inst/Equal.rgraynext_12_s1/I0
4.727	0.210	tINS	FR	5	R21C45[2][B]	your_instance_name/fifo_inst/Equal.rgraynext_12_s1/F
4.855	0.128	tNET	RR	1	R22C45[2][A]	your_instance_name/fifo_inst/Equal.rgraynext_12_s0/I0
5.268	0.413	tINS	RR	2	R22C45[2][A]	your_instance_name/fifo_inst/Equal.rgraynext_12_s0/F
5.960	0.692	tNET	RR	2	R22C45[0][A]	your_instance_name/fifo_inst/n153_s0/I0
6.405	0.445	tINS	RF	1	R22C45[0][A]	your_instance_name/fifo_inst/n153_s0/COUT
6.405	0.000	tNET	FF	2	R22C45[0][B]	your_instance_name/fifo_inst/n154_s0/CIN
6.445	0.040	tINS	FR	1	R22C45[0][B]	your_instance_name/fifo_inst/n154_s0/COUT
6.783	0.338	tNET	RR	1	R22C47[0][B]	your_instance_name/fifo_inst/rempty_val_s1/I0
6.993	0.210	tINS	RR	1	R22C47[0][B]	your_instance_name/fifo_inst/rempty_val_s1/F
6.993	0.000	tNET	RR	1	R22C47[0][B]	your_instance_name/fifo_inst/Empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.148	1.561	tNET	RR	1	R22C47[0][B]	your_instance_name/fifo_inst/Empty_s0/CLK
12.097	-0.051	tSu		1	R22C47[0][B]	your_instance_name/fifo_inst/Empty_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.587, 27.326%; route: 1.561, 72.674%
Arrival Data Path Delay	cell: 2.346, 48.421%; route: 2.193, 45.263%; tC2Q: 0.306, 6.316%
Required Clock Path Delay	cell: 0.587, 27.326%; route: 1.561, 72.674%

Path4

Path Summary:

Slack	5.140
Data Arrival Time	6.976
Data Required Time	12.115
From	your_instance_name/fifo_inst/Equal.wbin_1_s0
To	your_instance_name/fifo_inst/Full_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.150	1.563	tNET	RR	1	R21C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_1_s0/CLK
2.456	0.306	tC2Q	RR	19	R21C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_1_s0/Q
3.052	0.596	tNET	RR	1	R18C46[3][B]	your_instance_name/fifo_inst/Equal.wgraynext_2_s1/I3
3.450	0.398	tINS	RR	22	R18C46[3][B]	your_instance_name/fifo_inst/Equal.wgraynext_2_s1/F
4.786	1.336	tNET	RR	1	R23C44[3][B]	your_instance_name/fifo_inst/Equal.wbinnext_9_s4/I2
5.184	0.398	tINS	RR	3	R23C44[3][B]	your_instance_name/fifo_inst/Equal.wbinnext_9_s4/F
5.618	0.434	tNET	RR	1	R25C46[1][A]	your_instance_name/fifo_inst/wfull_val_s8/I0
5.987	0.369	tINS	RR	1	R25C46[1][A]	your_instance_name/fifo_inst/wfull_val_s8/F
6.097	0.110	tNET	RR	1	R25C46[2][A]	your_instance_name/fifo_inst/wfull_val_s2/I1
6.518	0.421	tINS	RR	1	R25C46[2][A]	your_instance_name/fifo_inst/wfull_val_s2/F
6.644	0.126	tNET	RR	1	R24C46[3][A]	your_instance_name/fifo_inst/wfull_val_s0/I1
6.976	0.332	tINS	RR	1	R24C46[3][A]	your_instance_name/fifo_inst/wfull_val_s0/F
6.976	0.000	tNET	RR	1	R24C46[3][A]	your_instance_name/fifo_inst/Full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.166	1.579	tNET	RR	1	R24C46[3][A]	your_instance_name/fifo_inst/Full_s0/CLK
12.115	-0.051	tSu		1	R24C46[3][A]	your_instance_name/fifo_inst/Full_s0

Path Statistics:

Clock Skew	0.016
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%
Arrival Data Path Delay	cell: 1.918, 39.743%; route: 2.602, 53.916%; tC2Q: 0.306, 6.341%
Required Clock Path Delay	cell: 0.587, 27.093%; route: 1.579, 72.907%

Path5

Path Summary:

Slack	5.201
Data Arrival Time	6.676
Data Required Time	11.877
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
6.676	2.496	tNET	RR	1	IOB87[A]	ad7606_driver/data_mult_ch_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.126	1.539	tNET	RR	1	IOB87[A]	ad7606_driver/data_mult_ch_9_s0/CLK
11.877	-0.249	tSu		1	IOB87[A]	ad7606_driver/data_mult_ch_9_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 22.774%; route: 3.219, 70.763%; tC2Q: 0.294, 6.463%
Required Clock Path Delay	cell: 0.587, 27.609%; route: 1.539, 72.391%

Path6

Path Summary:

Slack	5.332
Data Arrival Time	6.742
Data Required Time	12.073
From	your_instance_name/fifo_inst/Equal.wbin_1_s0
To	your_instance_name/fifo_inst/Equal.wptr_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.150	1.563	tNET	RR	1	R21C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_1_s0/CLK
2.456	0.306	tC2Q	RR	19	R21C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_1_s0/Q
3.052	0.596	tNET	RR	1	R18C46[3][B]	your_instance_name/fifo_inst/Equal.wgraynext_2_s1/I3
3.450	0.398	tINS	RR	22	R18C46[3][B]	your_instance_name/fifo_inst/Equal.wgraynext_2_s1/F
4.786	1.336	tNET	RR	1	R23C44[3][B]	your_instance_name/fifo_inst/Equal.wbinnext_9_s4/I2
5.184	0.398	tINS	RR	3	R23C44[3][B]	your_instance_name/fifo_inst/Equal.wbinnext_9_s4/F
5.464	0.280	tNET	RR	1	R22C43[3][A]	your_instance_name/fifo_inst/Equal.wbinnext_9_s6/I0
5.881	0.417	tINS	RR	2	R22C43[3][A]	your_instance_name/fifo_inst/Equal.wbinnext_9_s6/F
6.321	0.440	tNET	RR	1	R18C43[1][B]	your_instance_name/fifo_inst/Equal.wgraynext_9_s0/I1
6.742	0.421	tINS	RR	1	R18C43[1][B]	your_instance_name/fifo_inst/Equal.wgraynext_9_s0/F
6.742	0.000	tNET	RR	1	R18C43[1][B]	your_instance_name/fifo_inst/Equal.wptr_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.124	1.538	tNET	RR	1	R18C43[1][B]	your_instance_name/fifo_inst/Equal.wptr_9_s0/CLK
12.073	-0.051	tSu		1	R18C43[1][B]	your_instance_name/fifo_inst/Equal.wptr_9_s0

Path Statistics:

Clock Skew	-0.025
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%
Arrival Data Path Delay	cell: 1.634, 35.584%; route: 2.652, 57.753%; tC2Q: 0.306, 6.664%
Required Clock Path Delay	cell: 0.587, 27.628%; route: 1.538, 72.372%

Path7

Path Summary:

Slack	5.514
Data Arrival Time	6.370
Data Required Time	11.884
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
6.370	2.190	tNET	RR	1	IOB81[B]	ad7606_driver/data_mult_ch_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.133	1.546	tNET	RR	1	IOB81[B]	ad7606_driver/data_mult_ch_3_s0/CLK
11.884	-0.249	tSu		1	IOB81[B]	ad7606_driver/data_mult_ch_3_s0

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 24.417%; route: 2.913, 68.654%; tC2Q: 0.294, 6.929%
Required Clock Path Delay	cell: 0.587, 27.512%; route: 1.546, 72.488%

Path8

Path Summary:

Slack	5.706
Data Arrival Time	6.186
Data Required Time	11.892
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_4_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
6.186	2.006	tNET	RR	1	IOB81[A]	ad7606_driver/data_mult_ch_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.141	1.554	tNET	RR	1	IOB81[A]	ad7606_driver/data_mult_ch_4_s0/CLK
11.892	-0.249	tSu		1	IOB81[A]	ad7606_driver/data_mult_ch_4_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 25.524%; route: 2.729, 67.233%; tC2Q: 0.294, 7.243%
Required Clock Path Delay	cell: 0.587, 27.415%; route: 1.554, 72.585%

Path9

Path Summary:

Slack	5.735
Data Arrival Time	6.142
Data Required Time	11.877
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
6.142	1.962	tNET	RR	1	IOB75[A]	ad7606_driver/data_mult_ch_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.126	1.539	tNET	RR	1	IOB75[A]	ad7606_driver/data_mult_ch_2_s0/CLK
11.877	-0.249	tSu		1	IOB75[A]	ad7606_driver/data_mult_ch_2_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 25.803%; route: 2.685, 66.874%; tC2Q: 0.294, 7.323%
Required Clock Path Delay	cell: 0.587, 27.609%; route: 1.539, 72.391%

Path10

Path Summary:

Slack	5.742
Data Arrival Time	6.142
Data Required Time	11.884
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
6.142	1.962	tNET	RR	1	IOB75[B]	ad7606_driver/data_mult_ch_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.133	1.546	tNET	RR	1	IOB75[B]	ad7606_driver/data_mult_ch_1_s0/CLK
11.884	-0.249	tSu		1	IOB75[B]	ad7606_driver/data_mult_ch_1_s0

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 25.803%; route: 2.685, 66.874%; tC2Q: 0.294, 7.323%
Required Clock Path Delay	cell: 0.587, 27.512%; route: 1.546, 72.488%

Path11

Path Summary:

Slack	5.796
Data Arrival Time	6.084
Data Required Time	11.880
From	ad7606_driver/cnt_2_s0
To	ad7606_driver/Conv_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C50[2][B]	ad7606_driver/cnt_2_s0/CLK
2.433	0.306	tC2Q	RR	4	R15C50[2][B]	ad7606_driver/cnt_2_s0/Q
3.146	0.713	tNET	RR	2	R16C44[1][A]	ad7606_driver/n135_s0/I0
3.591	0.445	tINS	RF	1	R16C44[1][A]	ad7606_driver/n135_s0/COUT
3.591	0.000	tNET	FF	2	R16C44[1][B]	ad7606_driver/n136_s0/CIN
3.631	0.040	tINS	FR	1	R16C44[1][B]	ad7606_driver/n136_s0/COUT
3.631	0.000	tNET	RR	2	R16C44[2][A]	ad7606_driver/n137_s0/CIN
3.671	0.040	tINS	RR	1	R16C44[2][A]	ad7606_driver/n137_s0/COUT
3.671	0.000	tNET	RR	2	R16C44[2][B]	ad7606_driver/n138_s0/CIN
3.711	0.040	tINS	RR	1	R16C44[2][B]	ad7606_driver/n138_s0/COUT
3.711	0.000	tNET	RR	2	R16C45[0][A]	ad7606_driver/n139_s0/CIN
3.751	0.040	tINS	RR	1	R16C45[0][A]	ad7606_driver/n139_s0/COUT
3.751	0.000	tNET	RR	2	R16C45[0][B]	ad7606_driver/n140_s0/CIN
3.791	0.040	tINS	RR	1	R16C45[0][B]	ad7606_driver/n140_s0/COUT
3.791	0.000	tNET	RR	2	R16C45[1][A]	ad7606_driver/n141_s0/CIN
3.831	0.040	tINS	RR	1	R16C45[1][A]	ad7606_driver/n141_s0/COUT
3.831	0.000	tNET	RR	2	R16C45[1][B]	ad7606_driver/n142_s0/CIN
3.871	0.040	tINS	RR	1	R16C45[1][B]	ad7606_driver/n142_s0/COUT
3.871	0.000	tNET	RR	2	R16C45[2][A]	ad7606_driver/n143_s0/CIN
3.911	0.040	tINS	RR	1	R16C45[2][A]	ad7606_driver/n143_s0/COUT
3.911	0.000	tNET	RR	2	R16C45[2][B]	ad7606_driver/n144_s0/CIN
3.951	0.040	tINS	RR	1	R16C45[2][B]	ad7606_driver/n144_s0/COUT
3.951	0.000	tNET	RR	2	R16C46[0][A]	ad7606_driver/n145_s0/CIN
3.991	0.040	tINS	RR	1	R16C46[0][A]	ad7606_driver/n145_s0/COUT
3.991	0.000	tNET	RR	2	R16C46[0][B]	ad7606_driver/n146_s0/CIN
4.031	0.040	tINS	RR	1	R16C46[0][B]	ad7606_driver/n146_s0/COUT
4.031	0.000	tNET	RR	2	R16C46[1][A]	ad7606_driver/n147_s0/CIN
4.071	0.040	tINS	RR	1	R16C46[1][A]	ad7606_driver/n147_s0/COUT
4.071	0.000	tNET	RR	2	R16C46[1][B]	ad7606_driver/n148_s0/CIN
4.111	0.040	tINS	RR	1	R16C46[1][B]	ad7606_driver/n148_s0/COUT
4.111	0.000	tNET	RR	2	R16C46[2][A]	ad7606_driver/n149_s0/CIN
4.151	0.040	tINS	RR	1	R16C46[2][A]	ad7606_driver/n149_s0/COUT
4.151	0.000	tNET	RR	2	R16C46[2][B]	ad7606_driver/n150_s0/CIN
4.191	0.040	tINS	RR	1	R16C46[2][B]	ad7606_driver/n150_s0/COUT
4.191	0.000	tNET	RR	2	R16C47[0][A]	ad7606_driver/n151_s0/CIN
4.231	0.040	tINS	RR	1	R16C47[0][A]	ad7606_driver/n151_s0/COUT
4.231	0.000	tNET	RR	2	R16C47[0][B]	ad7606_driver/n152_s0/CIN
4.271	0.040	tINS	RR	1	R16C47[0][B]	ad7606_driver/n152_s0/COUT
4.271	0.000	tNET	RR	2	R16C47[1][A]	ad7606_driver/n153_s0/CIN
4.311	0.040	tINS	RR	1	R16C47[1][A]	ad7606_driver/n153_s0/COUT
4.311	0.000	tNET	RR	2	R16C47[1][B]	ad7606_driver/n154_s0/CIN
4.351	0.040	tINS	RR	1	R16C47[1][B]	ad7606_driver/n154_s0/COUT
4.351	0.000	tNET	RR	2	R16C47[2][A]	ad7606_driver/n155_s0/CIN
4.391	0.040	tINS	RR	1	R16C47[2][A]	ad7606_driver/n155_s0/COUT
4.391	0.000	tNET	RR	2	R16C47[2][B]	ad7606_driver/n156_s0/CIN
4.431	0.040	tINS	RR	1	R16C47[2][B]	ad7606_driver/n156_s0/COUT
4.431	0.000	tNET	RR	2	R16C48[0][A]	ad7606_driver/n157_s0/CIN
4.471	0.040	tINS	RR	28	R16C48[0][A]	ad7606_driver/n157_s0/COUT
5.265	0.794	tNET	RR	1	R16C53[1][B]	ad7606_driver/n934_s14/I0
5.634	0.369	tINS	RR	2	R16C53[1][B]	ad7606_driver/n934_s14/F
5.762	0.128	tNET	RR	1	R16C54[3][B]	ad7606_driver/Conv_s6/I0
5.974	0.212	tINS	RR	1	R16C54[3][B]	ad7606_driver/Conv_s6/F
6.084	0.110	tNET	RR	1	R16C54[1][A]	ad7606_driver/Conv_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.129	1.542	tNET	RR	1	R16C54[1][A]	ad7606_driver/Conv_s2/CLK
11.880	-0.249	tSu		1	R16C54[1][A]	ad7606_driver/Conv_s2

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.906, 48.168%; route: 1.745, 44.099%; tC2Q: 0.306, 7.733%
Required Clock Path Delay	cell: 0.587, 27.570%; route: 1.542, 72.430%

Path12

Path Summary:

Slack	5.880
Data Arrival Time	6.219
Data Required Time	12.099
From	your_instance_name/fifo_inst/Equal.wbin_1_s0
To	your_instance_name/fifo_inst/Equal.wbin_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.150	1.563	tNET	RR	1	R21C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_1_s0/CLK
2.456	0.306	tC2Q	RR	19	R21C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_1_s0/Q
3.052	0.596	tNET	RR	1	R18C46[3][B]	your_instance_name/fifo_inst/Equal.wgraynext_2_s1/I3
3.450	0.398	tINS	RR	22	R18C46[3][B]	your_instance_name/fifo_inst/Equal.wgraynext_2_s1/F
4.786	1.336	tNET	RR	1	R23C44[3][B]	your_instance_name/fifo_inst/Equal.wbinnext_9_s4/I2
5.184	0.398	tINS	RR	3	R23C44[3][B]	your_instance_name/fifo_inst/Equal.wbinnext_9_s4/F
5.464	0.280	tNET	RR	1	R22C43[3][A]	your_instance_name/fifo_inst/Equal.wbinnext_9_s6/I0
5.881	0.417	tINS	RR	2	R22C43[3][A]	your_instance_name/fifo_inst/Equal.wbinnext_9_s6/F
6.219	0.338	tNET	RR	1	R21C43[0][B]	your_instance_name/fifo_inst/Equal.wbin_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.150	1.563	tNET	RR	1	R21C43[0][B]	your_instance_name/fifo_inst/Equal.wbin_9_s0/CLK
12.099	-0.051	tSu		1	R21C43[0][B]	your_instance_name/fifo_inst/Equal.wbin_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%
Arrival Data Path Delay	cell: 1.213, 29.811%; route: 2.550, 62.669%; tC2Q: 0.306, 7.520%
Required Clock Path Delay	cell: 0.587, 27.301%; route: 1.563, 72.699%

Path13

Path Summary:

Slack	5.963
Data Arrival Time	5.949
Data Required Time	11.912
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/cmdvalid_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[0][B]	uart_cmd/cmdvalid_s3/I0
5.367	0.421	tINS	RR	1	R23C49[0][B]	uart_cmd/cmdvalid_s3/F
5.949	0.582	tNET	RR	1	R23C49[0][A]	uart_cmd/cmdvalid_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.161	1.574	tNET	RR	1	R23C49[0][A]	uart_cmd/cmdvalid_s1/CLK
11.912	-0.249	tSu		1	R23C49[0][A]	uart_cmd/cmdvalid_s1

Path Statistics:

Clock Skew	0.041
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.616, 42.204%; route: 1.907, 49.804%; tC2Q: 0.306, 7.992%
Required Clock Path Delay	cell: 0.587, 27.162%; route: 1.574, 72.838%

Path14

Path Summary:

Slack	5.971
Data Arrival Time	6.116
Data Required Time	12.087
From	ad7606_driver/cnt_2_s0
To	ad7606_driver/ad7606_convst_o_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C50[2][B]	ad7606_driver/cnt_2_s0/CLK
2.433	0.306	tC2Q	RR	4	R15C50[2][B]	ad7606_driver/cnt_2_s0/Q
3.146	0.713	tNET	RR	2	R16C44[1][A]	ad7606_driver/n135_s0/I0
3.591	0.445	tINS	RF	1	R16C44[1][A]	ad7606_driver/n135_s0/COUT
3.591	0.000	tNET	FF	2	R16C44[1][B]	ad7606_driver/n136_s0/CIN
3.631	0.040	tINS	FR	1	R16C44[1][B]	ad7606_driver/n136_s0/COUT
3.631	0.000	tNET	RR	2	R16C44[2][A]	ad7606_driver/n137_s0/CIN
3.671	0.040	tINS	RR	1	R16C44[2][A]	ad7606_driver/n137_s0/COUT
3.671	0.000	tNET	RR	2	R16C44[2][B]	ad7606_driver/n138_s0/CIN
3.711	0.040	tINS	RR	1	R16C44[2][B]	ad7606_driver/n138_s0/COUT
3.711	0.000	tNET	RR	2	R16C45[0][A]	ad7606_driver/n139_s0/CIN
3.751	0.040	tINS	RR	1	R16C45[0][A]	ad7606_driver/n139_s0/COUT
3.751	0.000	tNET	RR	2	R16C45[0][B]	ad7606_driver/n140_s0/CIN
3.791	0.040	tINS	RR	1	R16C45[0][B]	ad7606_driver/n140_s0/COUT
3.791	0.000	tNET	RR	2	R16C45[1][A]	ad7606_driver/n141_s0/CIN
3.831	0.040	tINS	RR	1	R16C45[1][A]	ad7606_driver/n141_s0/COUT
3.831	0.000	tNET	RR	2	R16C45[1][B]	ad7606_driver/n142_s0/CIN
3.871	0.040	tINS	RR	1	R16C45[1][B]	ad7606_driver/n142_s0/COUT
3.871	0.000	tNET	RR	2	R16C45[2][A]	ad7606_driver/n143_s0/CIN
3.911	0.040	tINS	RR	1	R16C45[2][A]	ad7606_driver/n143_s0/COUT
3.911	0.000	tNET	RR	2	R16C45[2][B]	ad7606_driver/n144_s0/CIN
3.951	0.040	tINS	RR	1	R16C45[2][B]	ad7606_driver/n144_s0/COUT
3.951	0.000	tNET	RR	2	R16C46[0][A]	ad7606_driver/n145_s0/CIN
3.991	0.040	tINS	RR	1	R16C46[0][A]	ad7606_driver/n145_s0/COUT
3.991	0.000	tNET	RR	2	R16C46[0][B]	ad7606_driver/n146_s0/CIN
4.031	0.040	tINS	RR	1	R16C46[0][B]	ad7606_driver/n146_s0/COUT
4.031	0.000	tNET	RR	2	R16C46[1][A]	ad7606_driver/n147_s0/CIN
4.071	0.040	tINS	RR	1	R16C46[1][A]	ad7606_driver/n147_s0/COUT
4.071	0.000	tNET	RR	2	R16C46[1][B]	ad7606_driver/n148_s0/CIN
4.111	0.040	tINS	RR	1	R16C46[1][B]	ad7606_driver/n148_s0/COUT
4.111	0.000	tNET	RR	2	R16C46[2][A]	ad7606_driver/n149_s0/CIN
4.151	0.040	tINS	RR	1	R16C46[2][A]	ad7606_driver/n149_s0/COUT
4.151	0.000	tNET	RR	2	R16C46[2][B]	ad7606_driver/n150_s0/CIN
4.191	0.040	tINS	RR	1	R16C46[2][B]	ad7606_driver/n150_s0/COUT
4.191	0.000	tNET	RR	2	R16C47[0][A]	ad7606_driver/n151_s0/CIN
4.231	0.040	tINS	RR	1	R16C47[0][A]	ad7606_driver/n151_s0/COUT
4.231	0.000	tNET	RR	2	R16C47[0][B]	ad7606_driver/n152_s0/CIN
4.271	0.040	tINS	RR	1	R16C47[0][B]	ad7606_driver/n152_s0/COUT
4.271	0.000	tNET	RR	2	R16C47[1][A]	ad7606_driver/n153_s0/CIN
4.311	0.040	tINS	RR	1	R16C47[1][A]	ad7606_driver/n153_s0/COUT
4.311	0.000	tNET	RR	2	R16C47[1][B]	ad7606_driver/n154_s0/CIN
4.351	0.040	tINS	RR	1	R16C47[1][B]	ad7606_driver/n154_s0/COUT
4.351	0.000	tNET	RR	2	R16C47[2][A]	ad7606_driver/n155_s0/CIN
4.391	0.040	tINS	RR	1	R16C47[2][A]	ad7606_driver/n155_s0/COUT
4.391	0.000	tNET	RR	2	R16C47[2][B]	ad7606_driver/n156_s0/CIN
4.431	0.040	tINS	RR	1	R16C47[2][B]	ad7606_driver/n156_s0/COUT
4.431	0.000	tNET	RR	2	R16C48[0][A]	ad7606_driver/n157_s0/CIN
4.471	0.040	tINS	RF	28	R16C48[0][A]	ad7606_driver/n157_s0/COUT
5.277	0.806	tNET	FF	1	R16C54[3][A]	ad7606_driver/n922_s7/I0
5.509	0.232	tINS	FF	1	R16C54[3][A]	ad7606_driver/n922_s7/F
6.116	0.607	tNET	FF	1	IOB56[A]	ad7606_driver/ad7606_convst_o_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.133	1.546	tNET	RR	1	IOB56[A]	ad7606_driver/ad7606_convst_o_s1/CLK
12.087	-0.046	tSu		1	IOB56[A]	ad7606_driver/ad7606_convst_o_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.557, 39.032%; route: 2.126, 53.297%; tC2Q: 0.306, 7.671%
Required Clock Path Delay	cell: 0.587, 27.512%; route: 1.546, 72.488%

Path15

Path Summary:

Slack	6.002
Data Arrival Time	6.076
Data Required Time	12.078
From	ad7606_driver/cnt_2_s0
To	ad7606_driver/state_0_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C50[2][B]	ad7606_driver/cnt_2_s0/CLK
2.433	0.306	tC2Q	RR	4	R15C50[2][B]	ad7606_driver/cnt_2_s0/Q
3.146	0.713	tNET	RR	2	R16C44[1][A]	ad7606_driver/n135_s0/I0
3.591	0.445	tINS	RF	1	R16C44[1][A]	ad7606_driver/n135_s0/COUT
3.591	0.000	tNET	FF	2	R16C44[1][B]	ad7606_driver/n136_s0/CIN
3.631	0.040	tINS	FR	1	R16C44[1][B]	ad7606_driver/n136_s0/COUT
3.631	0.000	tNET	RR	2	R16C44[2][A]	ad7606_driver/n137_s0/CIN
3.671	0.040	tINS	RR	1	R16C44[2][A]	ad7606_driver/n137_s0/COUT
3.671	0.000	tNET	RR	2	R16C44[2][B]	ad7606_driver/n138_s0/CIN
3.711	0.040	tINS	RR	1	R16C44[2][B]	ad7606_driver/n138_s0/COUT
3.711	0.000	tNET	RR	2	R16C45[0][A]	ad7606_driver/n139_s0/CIN
3.751	0.040	tINS	RR	1	R16C45[0][A]	ad7606_driver/n139_s0/COUT
3.751	0.000	tNET	RR	2	R16C45[0][B]	ad7606_driver/n140_s0/CIN
3.791	0.040	tINS	RR	1	R16C45[0][B]	ad7606_driver/n140_s0/COUT
3.791	0.000	tNET	RR	2	R16C45[1][A]	ad7606_driver/n141_s0/CIN
3.831	0.040	tINS	RR	1	R16C45[1][A]	ad7606_driver/n141_s0/COUT
3.831	0.000	tNET	RR	2	R16C45[1][B]	ad7606_driver/n142_s0/CIN
3.871	0.040	tINS	RR	1	R16C45[1][B]	ad7606_driver/n142_s0/COUT
3.871	0.000	tNET	RR	2	R16C45[2][A]	ad7606_driver/n143_s0/CIN
3.911	0.040	tINS	RR	1	R16C45[2][A]	ad7606_driver/n143_s0/COUT
3.911	0.000	tNET	RR	2	R16C45[2][B]	ad7606_driver/n144_s0/CIN
3.951	0.040	tINS	RR	1	R16C45[2][B]	ad7606_driver/n144_s0/COUT
3.951	0.000	tNET	RR	2	R16C46[0][A]	ad7606_driver/n145_s0/CIN
3.991	0.040	tINS	RR	1	R16C46[0][A]	ad7606_driver/n145_s0/COUT
3.991	0.000	tNET	RR	2	R16C46[0][B]	ad7606_driver/n146_s0/CIN
4.031	0.040	tINS	RR	1	R16C46[0][B]	ad7606_driver/n146_s0/COUT
4.031	0.000	tNET	RR	2	R16C46[1][A]	ad7606_driver/n147_s0/CIN
4.071	0.040	tINS	RR	1	R16C46[1][A]	ad7606_driver/n147_s0/COUT
4.071	0.000	tNET	RR	2	R16C46[1][B]	ad7606_driver/n148_s0/CIN
4.111	0.040	tINS	RR	1	R16C46[1][B]	ad7606_driver/n148_s0/COUT
4.111	0.000	tNET	RR	2	R16C46[2][A]	ad7606_driver/n149_s0/CIN
4.151	0.040	tINS	RR	1	R16C46[2][A]	ad7606_driver/n149_s0/COUT
4.151	0.000	tNET	RR	2	R16C46[2][B]	ad7606_driver/n150_s0/CIN
4.191	0.040	tINS	RR	1	R16C46[2][B]	ad7606_driver/n150_s0/COUT
4.191	0.000	tNET	RR	2	R16C47[0][A]	ad7606_driver/n151_s0/CIN
4.231	0.040	tINS	RR	1	R16C47[0][A]	ad7606_driver/n151_s0/COUT
4.231	0.000	tNET	RR	2	R16C47[0][B]	ad7606_driver/n152_s0/CIN
4.271	0.040	tINS	RR	1	R16C47[0][B]	ad7606_driver/n152_s0/COUT
4.271	0.000	tNET	RR	2	R16C47[1][A]	ad7606_driver/n153_s0/CIN
4.311	0.040	tINS	RR	1	R16C47[1][A]	ad7606_driver/n153_s0/COUT
4.311	0.000	tNET	RR	2	R16C47[1][B]	ad7606_driver/n154_s0/CIN
4.351	0.040	tINS	RR	1	R16C47[1][B]	ad7606_driver/n154_s0/COUT
4.351	0.000	tNET	RR	2	R16C47[2][A]	ad7606_driver/n155_s0/CIN
4.391	0.040	tINS	RR	1	R16C47[2][A]	ad7606_driver/n155_s0/COUT
4.391	0.000	tNET	RR	2	R16C47[2][B]	ad7606_driver/n156_s0/CIN
4.431	0.040	tINS	RR	1	R16C47[2][B]	ad7606_driver/n156_s0/COUT
4.431	0.000	tNET	RR	2	R16C48[0][A]	ad7606_driver/n157_s0/CIN
4.471	0.040	tINS	RF	28	R16C48[0][A]	ad7606_driver/n157_s0/COUT
5.130	0.659	tNET	FF	1	R16C52[0][A]	ad7606_driver/n915_s67/I0
5.551	0.421	tINS	FR	2	R16C52[0][A]	ad7606_driver/n915_s67/F
5.663	0.112	tNET	RR	1	R16C52[1][B]	ad7606_driver/n919_s112/I2
6.076	0.413	tINS	RR	1	R16C52[1][B]	ad7606_driver/n919_s112/F
6.076	0.000	tNET	RR	1	R16C52[1][B]	ad7606_driver/state_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.129	1.542	tNET	RR	1	R16C52[1][B]	ad7606_driver/state_0_s1/CLK
12.078	-0.051	tSu		1	R16C52[1][B]	ad7606_driver/state_0_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 2.159, 54.672%; route: 1.484, 37.579%; tC2Q: 0.306, 7.749%
Required Clock Path Delay	cell: 0.587, 27.570%; route: 1.542, 72.430%

Path16

Path Summary:

Slack	6.041
Data Arrival Time	5.861
Data Required Time	11.902
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
5.861	1.681	tNET	RR	1	IOR5[B]	ad7606_driver/data_mult_ch_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.151	1.564	tNET	RR	1	IOR5[B]	ad7606_driver/data_mult_ch_11_s0/CLK
11.902	-0.249	tSu		1	IOR5[B]	ad7606_driver/data_mult_ch_11_s0

Path Statistics:

Clock Skew	0.024
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 27.745%; route: 2.404, 64.381%; tC2Q: 0.294, 7.874%
Required Clock Path Delay	cell: 0.587, 27.282%; route: 1.564, 72.718%

Path17

Path Summary:

Slack	6.043
Data Arrival Time	5.861
Data Required Time	11.904
From	ad7606_driver/state_2_s0
To	ad7606_driver/data_mult_ch_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
2.421	0.294	tC2Q	RF	20	R15C52[3][A]	ad7606_driver/state_2_s0/Q
2.876	0.455	tNET	FF	1	R14C53[0][B]	ad7606_driver/n781_s5/I3
3.289	0.413	tINS	FR	2	R14C53[0][B]	ad7606_driver/n781_s5/F
3.293	0.004	tNET	RR	1	R14C53[1][B]	ad7606_driver/n761_s5/I1
3.706	0.413	tINS	RR	2	R14C53[1][B]	ad7606_driver/n761_s5/F
3.970	0.264	tNET	RR	1	R16C53[0][B]	ad7606_driver/n97_s0/I3
4.180	0.210	tINS	RR	19	R16C53[0][B]	ad7606_driver/n97_s0/F
5.861	1.681	tNET	RR	1	IOR5[A]	ad7606_driver/data_mult_ch_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.153	1.566	tNET	RR	1	IOR5[A]	ad7606_driver/data_mult_ch_12_s0/CLK
11.904	-0.249	tSu		1	IOR5[A]	ad7606_driver/data_mult_ch_12_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 1.036, 27.745%; route: 2.404, 64.381%; tC2Q: 0.294, 7.874%
Required Clock Path Delay	cell: 0.587, 27.256%; route: 1.566, 72.744%

Path18

Path Summary:

Slack	6.047
Data Arrival Time	6.040
Data Required Time	12.087
From	uart_byte_tx/r_data_byte_3_s0
To	uart_byte_tx/Rs232_Tx_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.165	1.578	tNET	RR	1	R21C41[0][A]	uart_byte_tx/r_data_byte_3_s0/CLK
2.471	0.306	tC2Q	RR	1	R21C41[0][A]	uart_byte_tx/r_data_byte_3_s0/Q
2.777	0.306	tNET	RR	1	R24C41[2][A]	uart_byte_tx/n192_s33/I1
3.198	0.421	tINS	RR	1	R24C41[2][A]	uart_byte_tx/n192_s33/F
3.198	0.000	tNET	RR	1	R24C41[2][A]	uart_byte_tx/n192_s22/I0
3.307	0.109	tINS	RR	1	R24C41[2][A]	uart_byte_tx/n192_s22/O
3.433	0.126	tNET	RR	1	R24C41[3][A]	uart_byte_tx/n192_s35/I0
3.665	0.232	tINS	RF	1	R24C41[3][A]	uart_byte_tx/n192_s35/F
3.665	0.000	tNET	FF	1	R24C41[3][A]	uart_byte_tx/n192_s26/I0
3.822	0.157	tINS	FF	1	R24C41[3][A]	uart_byte_tx/n192_s26/O
4.059	0.237	tNET	FF	1	R24C40[0][B]	uart_byte_tx/n192_s28/I2
4.269	0.210	tINS	FR	1	R24C40[0][B]	uart_byte_tx/n192_s28/F
6.040	1.771	tNET	RR	1	IOR9[A]	uart_byte_tx/Rs232_Tx_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.138	1.551	tNET	RR	1	IOR9[A]	uart_byte_tx/Rs232_Tx_s0/CLK
12.087	-0.051	tSu		1	IOR9[A]	uart_byte_tx/Rs232_Tx_s0

Path Statistics:

Clock Skew	-0.027
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.587, 27.111%; route: 1.578, 72.889%
Arrival Data Path Delay	cell: 1.129, 29.135%; route: 2.440, 62.968%; tC2Q: 0.306, 7.897%
Required Clock Path Delay	cell: 0.587, 27.454%; route: 1.551, 72.546%

Path19

Path Summary:

Slack	6.065
Data Arrival Time	6.011
Data Required Time	12.076
From	ad7606_driver/cnt_2_s0
To	ad7606_driver/state_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.127	1.541	tNET	RR	1	R15C50[2][B]	ad7606_driver/cnt_2_s0/CLK
2.433	0.306	tC2Q	RR	4	R15C50[2][B]	ad7606_driver/cnt_2_s0/Q
3.146	0.713	tNET	RR	2	R16C44[1][A]	ad7606_driver/n135_s0/I0
3.591	0.445	tINS	RF	1	R16C44[1][A]	ad7606_driver/n135_s0/COUT
3.591	0.000	tNET	FF	2	R16C44[1][B]	ad7606_driver/n136_s0/CIN
3.631	0.040	tINS	FR	1	R16C44[1][B]	ad7606_driver/n136_s0/COUT
3.631	0.000	tNET	RR	2	R16C44[2][A]	ad7606_driver/n137_s0/CIN
3.671	0.040	tINS	RR	1	R16C44[2][A]	ad7606_driver/n137_s0/COUT
3.671	0.000	tNET	RR	2	R16C44[2][B]	ad7606_driver/n138_s0/CIN
3.711	0.040	tINS	RR	1	R16C44[2][B]	ad7606_driver/n138_s0/COUT
3.711	0.000	tNET	RR	2	R16C45[0][A]	ad7606_driver/n139_s0/CIN
3.751	0.040	tINS	RR	1	R16C45[0][A]	ad7606_driver/n139_s0/COUT
3.751	0.000	tNET	RR	2	R16C45[0][B]	ad7606_driver/n140_s0/CIN
3.791	0.040	tINS	RR	1	R16C45[0][B]	ad7606_driver/n140_s0/COUT
3.791	0.000	tNET	RR	2	R16C45[1][A]	ad7606_driver/n141_s0/CIN
3.831	0.040	tINS	RR	1	R16C45[1][A]	ad7606_driver/n141_s0/COUT
3.831	0.000	tNET	RR	2	R16C45[1][B]	ad7606_driver/n142_s0/CIN
3.871	0.040	tINS	RR	1	R16C45[1][B]	ad7606_driver/n142_s0/COUT
3.871	0.000	tNET	RR	2	R16C45[2][A]	ad7606_driver/n143_s0/CIN
3.911	0.040	tINS	RR	1	R16C45[2][A]	ad7606_driver/n143_s0/COUT
3.911	0.000	tNET	RR	2	R16C45[2][B]	ad7606_driver/n144_s0/CIN
3.951	0.040	tINS	RR	1	R16C45[2][B]	ad7606_driver/n144_s0/COUT
3.951	0.000	tNET	RR	2	R16C46[0][A]	ad7606_driver/n145_s0/CIN
3.991	0.040	tINS	RR	1	R16C46[0][A]	ad7606_driver/n145_s0/COUT
3.991	0.000	tNET	RR	2	R16C46[0][B]	ad7606_driver/n146_s0/CIN
4.031	0.040	tINS	RR	1	R16C46[0][B]	ad7606_driver/n146_s0/COUT
4.031	0.000	tNET	RR	2	R16C46[1][A]	ad7606_driver/n147_s0/CIN
4.071	0.040	tINS	RR	1	R16C46[1][A]	ad7606_driver/n147_s0/COUT
4.071	0.000	tNET	RR	2	R16C46[1][B]	ad7606_driver/n148_s0/CIN
4.111	0.040	tINS	RR	1	R16C46[1][B]	ad7606_driver/n148_s0/COUT
4.111	0.000	tNET	RR	2	R16C46[2][A]	ad7606_driver/n149_s0/CIN
4.151	0.040	tINS	RR	1	R16C46[2][A]	ad7606_driver/n149_s0/COUT
4.151	0.000	tNET	RR	2	R16C46[2][B]	ad7606_driver/n150_s0/CIN
4.191	0.040	tINS	RR	1	R16C46[2][B]	ad7606_driver/n150_s0/COUT
4.191	0.000	tNET	RR	2	R16C47[0][A]	ad7606_driver/n151_s0/CIN
4.231	0.040	tINS	RR	1	R16C47[0][A]	ad7606_driver/n151_s0/COUT
4.231	0.000	tNET	RR	2	R16C47[0][B]	ad7606_driver/n152_s0/CIN
4.271	0.040	tINS	RR	1	R16C47[0][B]	ad7606_driver/n152_s0/COUT
4.271	0.000	tNET	RR	2	R16C47[1][A]	ad7606_driver/n153_s0/CIN
4.311	0.040	tINS	RR	1	R16C47[1][A]	ad7606_driver/n153_s0/COUT
4.311	0.000	tNET	RR	2	R16C47[1][B]	ad7606_driver/n154_s0/CIN
4.351	0.040	tINS	RR	1	R16C47[1][B]	ad7606_driver/n154_s0/COUT
4.351	0.000	tNET	RR	2	R16C47[2][A]	ad7606_driver/n155_s0/CIN
4.391	0.040	tINS	RR	1	R16C47[2][A]	ad7606_driver/n155_s0/COUT
4.391	0.000	tNET	RR	2	R16C47[2][B]	ad7606_driver/n156_s0/CIN
4.431	0.040	tINS	RR	1	R16C47[2][B]	ad7606_driver/n156_s0/COUT
4.431	0.000	tNET	RR	2	R16C48[0][A]	ad7606_driver/n157_s0/CIN
4.471	0.040	tINS	RF	28	R16C48[0][A]	ad7606_driver/n157_s0/COUT
5.130	0.659	tNET	FF	1	R16C52[0][A]	ad7606_driver/n915_s67/I0
5.551	0.421	tINS	FR	2	R16C52[0][A]	ad7606_driver/n915_s67/F
5.679	0.128	tNET	RR	1	R15C52[3][A]	ad7606_driver/n915_s58/I3
6.011	0.332	tINS	RR	1	R15C52[3][A]	ad7606_driver/n915_s58/F
6.011	0.000	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.127	1.541	tNET	RR	1	R15C52[3][A]	ad7606_driver/state_2_s0/CLK
12.076	-0.051	tSu		1	R15C52[3][A]	ad7606_driver/state_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%
Arrival Data Path Delay	cell: 2.078, 53.502%; route: 1.500, 38.620%; tC2Q: 0.306, 7.878%
Required Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%

Path20

Path Summary:

Slack	6.088
Data Arrival Time	5.811
Data Required Time	11.899
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/data_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[3][B]	uart_cmd/n384_s0/I1
5.363	0.417	tINS	RR	33	R23C49[3][B]	uart_cmd/n384_s0/F
5.811	0.448	tNET	RR	1	R22C51[0][A]	uart_cmd/data_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.148	1.561	tNET	RR	1	R22C51[0][A]	uart_cmd/data_2_s0/CLK
11.899	-0.249	tSu		1	R22C51[0][A]	uart_cmd/data_2_s0

Path Statistics:

Clock Skew	0.028
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.612, 43.674%; route: 1.773, 48.036%; tC2Q: 0.306, 8.290%
Required Clock Path Delay	cell: 0.587, 27.326%; route: 1.561, 72.674%

Path21

Path Summary:

Slack	6.092
Data Arrival Time	5.811
Data Required Time	11.902
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/data_20_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[3][B]	uart_cmd/n384_s0/I1
5.363	0.417	tINS	RR	33	R23C49[3][B]	uart_cmd/n384_s0/F
5.811	0.448	tNET	RR	1	R24C48[0][B]	uart_cmd/data_20_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.151	1.564	tNET	RR	1	R24C48[0][B]	uart_cmd/data_20_s0/CLK
11.902	-0.249	tSu		1	R24C48[0][B]	uart_cmd/data_20_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.612, 43.674%; route: 1.773, 48.036%; tC2Q: 0.306, 8.290%
Required Clock Path Delay	cell: 0.587, 27.282%; route: 1.564, 72.718%

Path22

Path Summary:

Slack	6.092
Data Arrival Time	5.811
Data Required Time	11.902
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/data_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[3][B]	uart_cmd/n384_s0/I1
5.363	0.417	tINS	RR	33	R23C49[3][B]	uart_cmd/n384_s0/F
5.811	0.448	tNET	RR	1	R24C48[2][A]	uart_cmd/data_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.151	1.564	tNET	RR	1	R24C48[2][A]	uart_cmd/data_15_s0/CLK
11.902	-0.249	tSu		1	R24C48[2][A]	uart_cmd/data_15_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.612, 43.674%; route: 1.773, 48.036%; tC2Q: 0.306, 8.290%
Required Clock Path Delay	cell: 0.587, 27.282%; route: 1.564, 72.718%

Path23

Path Summary:

Slack	6.092
Data Arrival Time	5.811
Data Required Time	11.902
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/data_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[3][B]	uart_cmd/n384_s0/I1
5.363	0.417	tINS	RR	33	R23C49[3][B]	uart_cmd/n384_s0/F
5.811	0.448	tNET	RR	1	R24C48[2][B]	uart_cmd/data_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.151	1.564	tNET	RR	1	R24C48[2][B]	uart_cmd/data_14_s0/CLK
11.902	-0.249	tSu		1	R24C48[2][B]	uart_cmd/data_14_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.612, 43.674%; route: 1.773, 48.036%; tC2Q: 0.306, 8.290%
Required Clock Path Delay	cell: 0.587, 27.282%; route: 1.564, 72.718%

Path24

Path Summary:

Slack	6.092
Data Arrival Time	5.811
Data Required Time	11.902
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/data_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[3][B]	uart_cmd/n384_s0/I1
5.363	0.417	tINS	RR	33	R23C49[3][B]	uart_cmd/n384_s0/F
5.811	0.448	tNET	RR	1	R24C48[0][A]	uart_cmd/data_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.151	1.564	tNET	RR	1	R24C48[0][A]	uart_cmd/data_9_s0/CLK
11.902	-0.249	tSu		1	R24C48[0][A]	uart_cmd/data_9_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.612, 43.674%; route: 1.773, 48.036%; tC2Q: 0.306, 8.290%
Required Clock Path Delay	cell: 0.587, 27.282%; route: 1.564, 72.718%

Path25

Path Summary:

Slack	6.092
Data Arrival Time	5.811
Data Required Time	11.902
From	uart_cmd/data_str[7]_3_s0
To	uart_cmd/data_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
2.120	1.533	tNET	RR	1	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/CLK
2.426	0.306	tC2Q	RR	2	R15C47[2][A]	uart_cmd/data_str[7]_3_s0/Q
3.011	0.585	tNET	RR	1	R22C50[0][B]	uart_cmd/n384_s6/I3
3.424	0.413	tINS	RR	1	R22C50[0][B]	uart_cmd/n384_s6/F
3.854	0.430	tNET	RR	1	R25C51[2][A]	uart_cmd/n384_s3/I1
4.267	0.413	tINS	RR	1	R25C51[2][A]	uart_cmd/n384_s3/F
4.269	0.002	tNET	RR	1	R25C51[2][B]	uart_cmd/n384_s1/I3
4.638	0.369	tINS	RR	2	R25C51[2][B]	uart_cmd/n384_s1/F
4.946	0.308	tNET	RR	1	R23C49[3][B]	uart_cmd/n384_s0/I1
5.363	0.417	tINS	RR	33	R23C49[3][B]	uart_cmd/n384_s0/F
5.811	0.448	tNET	RR	1	R24C48[1][B]	uart_cmd/data_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					Clk
10.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
10.587	0.587	tINS	RR	506	IOB29[A]	Clk_ibuf/O
12.151	1.564	tNET	RR	1	R24C48[1][B]	uart_cmd/data_7_s0/CLK
11.902	-0.249	tSu		1	R24C48[1][B]	uart_cmd/data_7_s0

Path Statistics:

Clock Skew	0.032
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%
Arrival Data Path Delay	cell: 1.612, 43.674%; route: 1.773, 48.036%; tC2Q: 0.306, 8.290%
Required Clock Path Delay	cell: 0.587, 27.282%; route: 1.564, 72.718%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.193
Data Arrival Time	1.510
Data Required Time	1.317
From	adc_write_ctrl/fifowrdata_8_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.275	0.694	tNET	RR	1	R29C44[0][A]	adc_write_ctrl/fifowrdata_8_s0/CLK
1.416	0.141	tC2Q	RF	1	R29C44[0][A]	adc_write_ctrl/fifowrdata_8_s0/Q
1.510	0.094	tNET	FF	1	BSRAM_R28[13]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.280	0.699	tNET	RR	1	BSRAM_R28[13]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s/CLKA
1.317	0.037	tHld		1	BSRAM_R28[13]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.581, 45.388%; route: 0.699, 54.612%

Path2

Path Summary:

Slack	0.193
Data Arrival Time	1.510
Data Required Time	1.317
From	adc_write_ctrl/fifowrdata_4_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_4_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.275	0.694	tNET	RR	1	R29C38[0][A]	adc_write_ctrl/fifowrdata_4_s0/CLK
1.416	0.141	tC2Q	RF	1	R29C38[0][A]	adc_write_ctrl/fifowrdata_4_s0/Q
1.510	0.094	tNET	FF	1	BSRAM_R28[11]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_4_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.280	0.699	tNET	RR	1	BSRAM_R28[11]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_4_s/CLKA
1.317	0.037	tHld		1	BSRAM_R28[11]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_4_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.581, 45.388%; route: 0.699, 54.612%

Path3

Path Summary:

Slack	0.193
Data Arrival Time	1.506
Data Required Time	1.313
From	adc_write_ctrl/fifowrdata_2_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_2_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.271	0.690	tNET	RR	1	R29C35[0][A]	adc_write_ctrl/fifowrdata_2_s0/CLK
1.412	0.141	tC2Q	RF	1	R29C35[0][A]	adc_write_ctrl/fifowrdata_2_s0/Q
1.506	0.094	tNET	FF	1	BSRAM_R28[10]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.276	0.695	tNET	RR	1	BSRAM_R28[10]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA
1.313	0.037	tHld		1	BSRAM_R28[10]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_2_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.709%; route: 0.690, 54.291%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.581, 45.530%; route: 0.695, 54.470%

Path4

Path Summary:

Slack	0.193
Data Arrival Time	1.510
Data Required Time	1.317
From	adc_write_ctrl/fifowrdata_0_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.275	0.694	tNET	RR	1	R29C32[0][A]	adc_write_ctrl/fifowrdata_0_s0/CLK
1.416	0.141	tC2Q	RF	1	R29C32[0][A]	adc_write_ctrl/fifowrdata_0_s0/Q
1.510	0.094	tNET	FF	1	BSRAM_R28[9]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.280	0.699	tNET	RR	1	BSRAM_R28[9]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA
1.317	0.037	tHld		1	BSRAM_R28[9]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.581, 45.388%; route: 0.699, 54.612%

Path5

Path Summary:

Slack	0.193
Data Arrival Time	1.514
Data Required Time	1.321
From	adc_write_ctrl/fifowrdata_13_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.279	0.698	tNET	RR	1	R11C53[0][A]	adc_write_ctrl/fifowrdata_13_s0/CLK
1.420	0.141	tC2Q	RF	1	R11C53[0][A]	adc_write_ctrl/fifowrdata_13_s0/Q
1.514	0.094	tNET	FF	1	BSRAM_R10[16]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.284	0.703	tNET	RR	1	BSRAM_R10[16]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/CLKA
1.321	0.037	tHld		1	BSRAM_R10[16]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.423%; route: 0.698, 54.577%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.581, 45.246%; route: 0.703, 54.754%

Path6

Path Summary:

Slack	0.193
Data Arrival Time	1.514
Data Required Time	1.321
From	adc_write_ctrl/fifowrdata_6_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.279	0.698	tNET	RR	1	R29C41[0][A]	adc_write_ctrl/fifowrdata_6_s0/CLK
1.420	0.141	tC2Q	RF	1	R29C41[0][A]	adc_write_ctrl/fifowrdata_6_s0/Q
1.514	0.094	tNET	FF	1	BSRAM_R28[12]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.284	0.703	tNET	RR	1	BSRAM_R28[12]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s/CLKA
1.321	0.037	tHld		1	BSRAM_R28[12]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.423%; route: 0.698, 54.577%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.581, 45.246%; route: 0.703, 54.754%

Path7

Path Summary:

Slack	0.228
Data Arrival Time	1.547
Data Required Time	1.319
From	your_instance_name/fifo_inst/rbin_num_10_s0
To	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.304	0.723	tNET	RR	1	R20C44[1][A]	your_instance_name/fifo_inst/rbin_num_10_s0/CLK
1.445	0.141	tC2Q	RF	21	R20C44[1][A]	your_instance_name/fifo_inst/rbin_num_10_s0/Q
1.547	0.102	tNET	FF	1	BSRAM_R10[13]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.284	0.703	tNET	RR	1	BSRAM_R10[13]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s/CLKB
1.319	0.035	tHld		1	BSRAM_R10[13]	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 44.561%; route: 0.723, 55.439%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.102, 41.975%; tC2Q: 0.141, 58.025%
Required Clock Path Delay	cell: 0.581, 45.246%; route: 0.703, 54.754%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.583
Data Required Time	1.308
From	uart_byte_rx/r_data[0]_0_s0
To	uart_byte_rx/r_data[0]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.283	0.702	tNET	RR	1	R16C41[0][A]	uart_byte_rx/r_data[0]_0_s0/CLK
1.424	0.141	tC2Q	RF	3	R16C41[0][A]	uart_byte_rx/r_data[0]_0_s0/Q
1.430	0.006	tNET	FF	1	R16C41[0][A]	uart_byte_rx/n593_s5/I1
1.583	0.153	tINS	FF	1	R16C41[0][A]	uart_byte_rx/n593_s5/F
1.583	0.000	tNET	FF	1	R16C41[0][A]	uart_byte_rx/r_data[0]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.283	0.702	tNET	RR	1	R16C41[0][A]	uart_byte_rx/r_data[0]_0_s0/CLK
1.308	0.025	tHld		1	R16C41[0][A]	uart_byte_rx/r_data[0]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.273%; route: 0.702, 54.727%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.273%; route: 0.702, 54.727%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.579
Data Required Time	1.304
From	uart_byte_rx/r_data[0]_1_s0
To	uart_byte_rx/r_data[0]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.279	0.698	tNET	RR	1	R16C42[1][A]	uart_byte_rx/r_data[0]_1_s0/CLK
1.420	0.141	tC2Q	RF	2	R16C42[1][A]	uart_byte_rx/r_data[0]_1_s0/Q
1.426	0.006	tNET	FF	1	R16C42[1][A]	uart_byte_rx/n590_s6/I0
1.579	0.153	tINS	FF	1	R16C42[1][A]	uart_byte_rx/n590_s6/F
1.579	0.000	tNET	FF	1	R16C42[1][A]	uart_byte_rx/r_data[0]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.279	0.698	tNET	RR	1	R16C42[1][A]	uart_byte_rx/r_data[0]_1_s0/CLK
1.304	0.025	tHld		1	R16C42[1][A]	uart_byte_rx/r_data[0]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.414%; route: 0.698, 54.586%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.414%; route: 0.698, 54.586%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.578
Data Required Time	1.303
From	uart_byte_rx/r_data[5]_1_s0
To	uart_byte_rx/r_data[5]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C44[1][A]	uart_byte_rx/r_data[5]_1_s0/CLK
1.419	0.141	tC2Q	RF	2	R15C44[1][A]	uart_byte_rx/r_data[5]_1_s0/Q
1.425	0.006	tNET	FF	1	R15C44[1][A]	uart_byte_rx/n545_s6/I0
1.578	0.153	tINS	FF	1	R15C44[1][A]	uart_byte_rx/n545_s6/F
1.578	0.000	tNET	FF	1	R15C44[1][A]	uart_byte_rx/r_data[5]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C44[1][A]	uart_byte_rx/r_data[5]_1_s0/CLK
1.303	0.025	tHld		1	R15C44[1][A]	uart_byte_rx/r_data[5]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.578
Data Required Time	1.303
From	uart_byte_rx/r_data[5]_2_s0
To	uart_byte_rx/r_data[5]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C44[0][A]	uart_byte_rx/r_data[5]_2_s0/CLK
1.419	0.141	tC2Q	RF	2	R15C44[0][A]	uart_byte_rx/r_data[5]_2_s0/Q
1.425	0.006	tNET	FF	1	R15C44[0][A]	uart_byte_rx/n542_s5/I2
1.578	0.153	tINS	FF	1	R15C44[0][A]	uart_byte_rx/n542_s5/F
1.578	0.000	tNET	FF	1	R15C44[0][A]	uart_byte_rx/r_data[5]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C44[0][A]	uart_byte_rx/r_data[5]_2_s0/CLK
1.303	0.025	tHld		1	R15C44[0][A]	uart_byte_rx/r_data[5]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.574
Data Required Time	1.299
From	uart_byte_rx/div_cnt_2_s0
To	uart_byte_rx/div_cnt_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.274	0.693	tNET	RR	1	R13C41[1][A]	uart_byte_rx/div_cnt_2_s0/CLK
1.415	0.141	tC2Q	RF	5	R13C41[1][A]	uart_byte_rx/div_cnt_2_s0/Q
1.421	0.006	tNET	FF	1	R13C41[1][A]	uart_byte_rx/n75_s4/I0
1.574	0.153	tINS	FF	1	R13C41[1][A]	uart_byte_rx/n75_s4/F
1.574	0.000	tNET	FF	1	R13C41[1][A]	uart_byte_rx/div_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.274	0.693	tNET	RR	1	R13C41[1][A]	uart_byte_rx/div_cnt_2_s0/CLK
1.299	0.025	tHld		1	R13C41[1][A]	uart_byte_rx/div_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.601%; route: 0.693, 54.399%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 45.601%; route: 0.693, 54.399%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.600
Data Required Time	1.325
From	uart_byte_tx/div_cnt_3_s0
To	uart_byte_tx/div_cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.300	0.719	tNET	RR	1	R22C40[1][A]	uart_byte_tx/div_cnt_3_s0/CLK
1.441	0.141	tC2Q	RF	3	R22C40[1][A]	uart_byte_tx/div_cnt_3_s0/Q
1.447	0.006	tNET	FF	1	R22C40[1][A]	uart_byte_tx/n129_s2/I2
1.600	0.153	tINS	FF	1	R22C40[1][A]	uart_byte_tx/n129_s2/F
1.600	0.000	tNET	FF	1	R22C40[1][A]	uart_byte_tx/div_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.300	0.719	tNET	RR	1	R22C40[1][A]	uart_byte_tx/div_cnt_3_s0/CLK
1.325	0.025	tHld		1	R22C40[1][A]	uart_byte_tx/div_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.604
Data Required Time	1.329
From	uart_byte_tx/div_cnt_14_s0
To	uart_byte_tx/div_cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.304	0.723	tNET	RR	1	R22C41[0][A]	uart_byte_tx/div_cnt_14_s0/CLK
1.445	0.141	tC2Q	RF	3	R22C41[0][A]	uart_byte_tx/div_cnt_14_s0/Q
1.451	0.006	tNET	FF	1	R22C41[0][A]	uart_byte_tx/n118_s5/I0
1.604	0.153	tINS	FF	1	R22C41[0][A]	uart_byte_tx/n118_s5/F
1.604	0.000	tNET	FF	1	R22C41[0][A]	uart_byte_tx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.304	0.723	tNET	RR	1	R22C41[0][A]	uart_byte_tx/div_cnt_14_s0/CLK
1.329	0.025	tHld		1	R22C41[0][A]	uart_byte_tx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.544%; route: 0.723, 55.456%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 44.544%; route: 0.723, 55.456%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.598
Data Required Time	1.323
From	adc_write_ctrl/skip_cnt_1_s1
To	adc_write_ctrl/skip_cnt_1_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.298	0.717	tNET	RR	1	R21C51[0][A]	adc_write_ctrl/skip_cnt_1_s1/CLK
1.439	0.141	tC2Q	RF	4	R21C51[0][A]	adc_write_ctrl/skip_cnt_1_s1/Q
1.445	0.006	tNET	FF	1	R21C51[0][A]	adc_write_ctrl/n186_s2/I1
1.598	0.153	tINS	FF	1	R21C51[0][A]	adc_write_ctrl/n186_s2/F
1.598	0.000	tNET	FF	1	R21C51[0][A]	adc_write_ctrl/skip_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.298	0.717	tNET	RR	1	R21C51[0][A]	adc_write_ctrl/skip_cnt_1_s1/CLK
1.323	0.025	tHld		1	R21C51[0][A]	adc_write_ctrl/skip_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.758%; route: 0.717, 55.242%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 44.758%; route: 0.717, 55.242%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.606
Data Required Time	1.331
From	adc_write_ctrl/skip_cnt_3_s1
To	adc_write_ctrl/skip_cnt_3_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.306	0.725	tNET	RR	1	R21C49[1][A]	adc_write_ctrl/skip_cnt_3_s1/CLK
1.447	0.141	tC2Q	RF	2	R21C49[1][A]	adc_write_ctrl/skip_cnt_3_s1/Q
1.453	0.006	tNET	FF	1	R21C49[1][A]	adc_write_ctrl/n184_s2/I3
1.606	0.153	tINS	FF	1	R21C49[1][A]	adc_write_ctrl/n184_s2/F
1.606	0.000	tNET	FF	1	R21C49[1][A]	adc_write_ctrl/skip_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.306	0.725	tNET	RR	1	R21C49[1][A]	adc_write_ctrl/skip_cnt_3_s1/CLK
1.331	0.025	tHld		1	R21C49[1][A]	adc_write_ctrl/skip_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.581, 44.484%; route: 0.725, 55.516%

Path17

Path Summary:

Slack	0.278
Data Arrival Time	1.578
Data Required Time	1.300
From	uart_byte_rx/r_data[2]_0_s0
To	uart_byte_rx/r_data[2]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.275	0.694	tNET	RR	1	R16C43[0][A]	uart_byte_rx/r_data[2]_0_s0/CLK
1.416	0.141	tC2Q	RF	3	R16C43[0][A]	uart_byte_rx/r_data[2]_0_s0/Q
1.425	0.009	tNET	FF	1	R16C43[0][A]	uart_byte_rx/n575_s5/I1
1.578	0.153	tINS	FF	1	R16C43[0][A]	uart_byte_rx/n575_s5/F
1.578	0.000	tNET	FF	1	R16C43[0][A]	uart_byte_rx/r_data[2]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.275	0.694	tNET	RR	1	R16C43[0][A]	uart_byte_rx/r_data[2]_0_s0/CLK
1.300	0.025	tHld		1	R16C43[0][A]	uart_byte_rx/r_data[2]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.557%; route: 0.694, 54.443%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 45.557%; route: 0.694, 54.443%

Path18

Path Summary:

Slack	0.278
Data Arrival Time	1.588
Data Required Time	1.310
From	uart_byte_rx/div_cnt_0_s0
To	uart_byte_rx/div_cnt_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.285	0.705	tNET	RR	1	R15C46[0][A]	uart_byte_rx/div_cnt_0_s0/CLK
1.426	0.141	tC2Q	RF	9	R15C46[0][A]	uart_byte_rx/div_cnt_0_s0/Q
1.435	0.009	tNET	FF	1	R15C46[0][A]	uart_byte_rx/n77_s3/I0
1.588	0.153	tINS	FF	1	R15C46[0][A]	uart_byte_rx/n77_s3/F
1.588	0.000	tNET	FF	1	R15C46[0][A]	uart_byte_rx/div_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.285	0.705	tNET	RR	1	R15C46[0][A]	uart_byte_rx/div_cnt_0_s0/CLK
1.310	0.025	tHld		1	R15C46[0][A]	uart_byte_rx/div_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.193%; route: 0.705, 54.807%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 45.193%; route: 0.705, 54.807%

Path19

Path Summary:

Slack	0.278
Data Arrival Time	1.577
Data Required Time	1.299
From	uart_byte_rx/div_cnt_4_s0
To	uart_byte_rx/div_cnt_4_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.274	0.693	tNET	RR	1	R13C45[1][A]	uart_byte_rx/div_cnt_4_s0/CLK
1.415	0.141	tC2Q	RF	6	R13C45[1][A]	uart_byte_rx/div_cnt_4_s0/Q
1.424	0.009	tNET	FF	1	R13C45[1][A]	uart_byte_rx/n73_s2/I0
1.577	0.153	tINS	FF	1	R13C45[1][A]	uart_byte_rx/n73_s2/F
1.577	0.000	tNET	FF	1	R13C45[1][A]	uart_byte_rx/div_cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.274	0.693	tNET	RR	1	R13C45[1][A]	uart_byte_rx/div_cnt_4_s0/CLK
1.299	0.025	tHld		1	R13C45[1][A]	uart_byte_rx/div_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 45.601%; route: 0.693, 54.399%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 45.601%; route: 0.693, 54.399%

Path20

Path Summary:

Slack	0.278
Data Arrival Time	1.600
Data Required Time	1.322
From	uart_byte_tx/bps_cnt_3_s1
To	uart_byte_tx/bps_cnt_3_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.297	0.716	tNET	RR	1	R24C40[0][A]	uart_byte_tx/bps_cnt_3_s1/CLK
1.438	0.141	tC2Q	RF	4	R24C40[0][A]	uart_byte_tx/bps_cnt_3_s1/Q
1.447	0.009	tNET	FF	1	R24C40[0][A]	uart_byte_tx/n168_s2/I3
1.600	0.153	tINS	FF	1	R24C40[0][A]	uart_byte_tx/n168_s2/F
1.600	0.000	tNET	FF	1	R24C40[0][A]	uart_byte_tx/bps_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.297	0.716	tNET	RR	1	R24C40[0][A]	uart_byte_tx/bps_cnt_3_s1/CLK
1.322	0.025	tHld		1	R24C40[0][A]	uart_byte_tx/bps_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.801%; route: 0.716, 55.199%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.801%; route: 0.716, 55.199%

Path21

Path Summary:

Slack	0.278
Data Arrival Time	1.603
Data Required Time	1.325
From	uart_byte_tx/div_cnt_11_s0
To	uart_byte_tx/div_cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.300	0.719	tNET	RR	1	R22C40[0][A]	uart_byte_tx/div_cnt_11_s0/CLK
1.441	0.141	tC2Q	RF	4	R22C40[0][A]	uart_byte_tx/div_cnt_11_s0/Q
1.450	0.009	tNET	FF	1	R22C40[0][A]	uart_byte_tx/n121_s2/I2
1.603	0.153	tINS	FF	1	R22C40[0][A]	uart_byte_tx/n121_s2/F
1.603	0.000	tNET	FF	1	R22C40[0][A]	uart_byte_tx/div_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.300	0.719	tNET	RR	1	R22C40[0][A]	uart_byte_tx/div_cnt_11_s0/CLK
1.325	0.025	tHld		1	R22C40[0][A]	uart_byte_tx/div_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path22

Path Summary:

Slack	0.278
Data Arrival Time	1.605
Data Required Time	1.327
From	adc_write_ctrl/data_cnt_12_s1
To	adc_write_ctrl/data_cnt_12_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C52[0][A]	adc_write_ctrl/data_cnt_12_s1/CLK
1.443	0.141	tC2Q	RF	4	R21C52[0][A]	adc_write_ctrl/data_cnt_12_s1/Q
1.452	0.009	tNET	FF	1	R21C52[0][A]	adc_write_ctrl/n121_s1/I2
1.605	0.153	tINS	FF	1	R21C52[0][A]	adc_write_ctrl/n121_s1/F
1.605	0.000	tNET	FF	1	R21C52[0][A]	adc_write_ctrl/data_cnt_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.302	0.721	tNET	RR	1	R21C52[0][A]	adc_write_ctrl/data_cnt_12_s1/CLK
1.327	0.025	tHld		1	R21C52[0][A]	adc_write_ctrl/data_cnt_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.621%; route: 0.721, 55.379%

Path23

Path Summary:

Slack	0.278
Data Arrival Time	1.614
Data Required Time	1.336
From	your_instance_name/fifo_inst/Equal.wbin_7_s0
To	your_instance_name/fifo_inst/Equal.wbin_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.311	0.730	tNET	RR	1	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbin_7_s0/CLK
1.452	0.141	tC2Q	RF	24	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbin_7_s0/Q
1.461	0.009	tNET	FF	1	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbinnext_7_s4/I3
1.614	0.153	tINS	FF	1	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbinnext_7_s4/F
1.614	0.000	tNET	FF	1	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbin_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.311	0.730	tNET	RR	1	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbin_7_s0/CLK
1.336	0.025	tHld		1	R20C46[1][A]	your_instance_name/fifo_inst/Equal.wbin_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.306%; route: 0.730, 55.694%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.306%; route: 0.730, 55.694%

Path24

Path Summary:

Slack	0.278
Data Arrival Time	1.600
Data Required Time	1.322
From	your_instance_name/fifo_inst/Equal.wbin_8_s0
To	your_instance_name/fifo_inst/Equal.wbin_8_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.297	0.716	tNET	RR	1	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbin_8_s0/CLK
1.438	0.141	tC2Q	RF	22	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbin_8_s0/Q
1.447	0.009	tNET	FF	1	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbinnext_8_s5/I3
1.600	0.153	tINS	FF	1	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbinnext_8_s5/F
1.600	0.000	tNET	FF	1	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbin_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.297	0.716	tNET	RR	1	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbin_8_s0/CLK
1.322	0.025	tHld		1	R24C44[1][A]	your_instance_name/fifo_inst/Equal.wbin_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.801%; route: 0.716, 55.199%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.801%; route: 0.716, 55.199%

Path25

Path Summary:

Slack	0.278
Data Arrival Time	1.597
Data Required Time	1.319
From	your_instance_name/fifo_inst/Equal.wbin_11_s0
To	your_instance_name/fifo_inst/Equal.wbin_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.294	0.714	tNET	RR	1	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_11_s0/CLK
1.435	0.141	tC2Q	RF	23	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_11_s0/Q
1.444	0.009	tNET	FF	1	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbinnext_11_s3/I2
1.597	0.153	tINS	FF	1	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbinnext_11_s3/F
1.597	0.000	tNET	FF	1	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOB29[A]	Clk_ibuf/I
0.581	0.581	tINS	RR	506	IOB29[A]	Clk_ibuf/O
1.294	0.714	tNET	RR	1	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_11_s0/CLK
1.319	0.025	tHld		1	R23C43[0][A]	your_instance_name/fifo_inst/Equal.wbin_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.581, 44.879%; route: 0.714, 55.121%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.581, 44.879%; route: 0.714, 55.121%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW2

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_5_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_5_s/CLKA

MPW3

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_6_s/CLKA

MPW4

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/CLKA

MPW5

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_14_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_14_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_14_s/CLKA

MPW6

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKB

MPW7

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_7_s/CLKB

MPW8

MPW Summary:

Slack:	3.279
Actual Width:	4.141
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.143	1.552	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.284	0.703	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_8_s/CLKB

MPW9

MPW Summary:

Slack:	3.282
Actual Width:	4.144
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.135	1.544	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.280	0.699	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKA

MPW10

MPW Summary:

Slack:	3.282
Actual Width:	4.144
Required Width:	0.862
Type:	Low Pulse Width
Clock:	Clk
Objects:	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			Clk
5.000	0.000	tCL	FF	Clk_ibuf/I
5.591	0.591	tINS	FF	Clk_ibuf/O
7.135	1.544	tNET	FF	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	RR	Clk_ibuf/I
10.581	0.581	tINS	RR	Clk_ibuf/O
11.280	0.699	tNET	RR	your_instance_name/fifo_inst/Equal.mem_Equal.mem_0_13_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
506	Clk_d	4.750	1.588
66	rx_done	8.347	1.284
33	n384_3	6.088	0.465
28	n157_3	5.796	0.910
27	Equal.wbin[2]	6.356	2.154
27	Equal.wbin[6]	6.217	1.318
25	n248_3	7.619	0.306
24	state[0]	5.059	0.572
24	state[1]	4.874	0.592
24	Equal.wbin[7]	6.555	1.667

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R20C44	45.83%
R18C46	44.44%
R21C50	40.28%
R20C46	38.89%
R21C44	37.50%
R21C51	37.50%
R20C51	36.11%
R15C48	34.72%
R20C49	34.72%
R18C49	34.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command