Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\FX2_CDC_UART_SPI.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\SPI_Slave.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\Spi_Master_Ctrl.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\User_Param.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\byte_tx_control.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\fifo_1024x8.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\fx2_fifo_crtl.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\hc595_driver.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\hex8.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\uart_byte_rx.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\60k_FX2_CDC_UART_SPI\src\uart_byte_tx.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV60PG484AC1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Tue Aug 5 11:38:39 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FX2_CDC_UART_SPI |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.664s, Peak memory usage = 1733.219MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.157s, Peak memory usage = 1733.219MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 1733.219MB Optimizing Phase 2: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.332s, Peak memory usage = 1733.219MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 1733.219MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 1733.219MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 1733.219MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 1733.219MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.224s, Peak memory usage = 1733.219MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 1733.219MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 1733.219MB Tech-Mapping Phase 3: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s, Peak memory usage = 1733.219MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 1733.219MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 1733.219MB |
| Total Time and Memory Usage | CPU time = 0h 0m 19s, Elapsed time = 0h 0m 19s, Peak memory usage = 1733.219MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 35 |
| I/O Buf | 35 |
| IBUF | 12 |
| OBUF | 14 |
| TBUF | 1 |
| IOBUF | 8 |
| Register | 976 |
| DFFRE | 457 |
| DFFPE | 21 |
| DFFCE | 498 |
| LUT | 2959 |
| LUT2 | 324 |
| LUT3 | 885 |
| LUT4 | 1750 |
| ALU | 84 |
| ALU | 84 |
| INV | 8 |
| INV | 8 |
| BSRAM | 2 |
| SDPB | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3051(2967 LUT, 84 ALU) / 59904 | 6% |
| Register | 976 / 60780 | 2% |
| --Register as Latch | 0 / 60780 | 0% |
| --Register as FF | 976 / 60780 | 2% |
| BSRAM | 2 / 118 | 2% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | FX2_SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_SPI_SCLK_ibuf/I | ||
| 4 | hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | hex8/clk_1K_s1/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.000(MHz) | 148.451(MHz) | 8 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 12.245(MHz) | 91 | TOP |
| 3 | FX2_SPI_SCLK | 100.000(MHz) | 290.170(MHz) | 4 | TOP |
| 4 | hex8/clk_1K | 100.000(MHz) | 390.816(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -71.669 |
| Data Arrival Time | 81.980 |
| Data Required Time | 10.311 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_0_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.034 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.560 | 0.526 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 2.935 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.461 | 0.526 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 3.836 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.362 | 0.526 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 4.737 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.264 | 0.526 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 5.639 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.100 | 0.461 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 6.475 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 6.991 | 0.516 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 7.366 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 7.892 | 0.526 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 8.267 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 8.784 | 0.516 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 9.159 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 9.675 | 0.516 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 10.050 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 10.576 | 0.526 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 10.951 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 11.477 | 0.526 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 11.852 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 12.379 | 0.526 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 12.754 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 13.280 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 13.655 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 14.181 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 14.556 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 15.082 | 0.526 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 15.457 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 15.984 | 0.526 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 16.359 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 16.875 | 0.516 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 17.250 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 17.776 | 0.526 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 18.151 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 18.678 | 0.526 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 19.053 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 19.579 | 0.526 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 19.954 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 20.470 | 0.516 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 20.845 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 21.371 | 0.526 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 21.746 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 22.273 | 0.526 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 22.648 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 23.174 | 0.526 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 23.549 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 24.075 | 0.526 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 24.450 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 24.976 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 25.351 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 25.878 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 26.253 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 26.779 | 0.526 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 27.154 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 27.680 | 0.526 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 28.055 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 28.571 | 0.516 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 28.946 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 29.473 | 0.526 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 29.848 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 30.374 | 0.526 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 30.749 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 31.275 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 31.650 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 32.176 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 32.551 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 33.078 | 0.526 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 33.453 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 33.979 | 0.526 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 34.354 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 34.880 | 0.526 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 35.255 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 35.771 | 0.516 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 36.146 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 36.673 | 0.526 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 37.048 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 37.564 | 0.516 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 37.939 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 38.455 | 0.516 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 38.830 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 39.346 | 0.516 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 39.721 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 40.248 | 0.526 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 40.623 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 41.149 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 41.524 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 42.050 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 42.425 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 42.951 | 0.526 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 43.326 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 43.853 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 44.228 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 44.754 | 0.526 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 45.129 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 45.645 | 0.516 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 46.020 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 46.546 | 0.526 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 46.921 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 47.448 | 0.526 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 47.823 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 48.349 | 0.526 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 48.724 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 49.250 | 0.526 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 49.625 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 50.151 | 0.526 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 50.526 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 51.052 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 51.427 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 51.954 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 52.329 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 52.845 | 0.516 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 53.220 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 53.736 | 0.516 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 54.111 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s77/I0 |
| 54.637 | 0.526 | tINS | RR | 5 | uart_byte_tx/n56_s77/F |
| 55.012 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s45/I1 |
| 55.529 | 0.516 | tINS | RR | 3 | uart_byte_tx/n56_s45/F |
| 55.904 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s29/I0 |
| 56.430 | 0.526 | tINS | RR | 2 | uart_byte_tx/n56_s29/F |
| 56.805 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s23/I0 |
| 57.331 | 0.526 | tINS | RR | 4 | uart_byte_tx/n56_s23/F |
| 57.706 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s21/I0 |
| 58.232 | 0.526 | tINS | RR | 14 | uart_byte_tx/n56_s21/F |
| 58.607 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n31_s52/I0 |
| 59.134 | 0.526 | tINS | RR | 22 | Spi_Master_Ctrl/n31_s52/F |
| 59.509 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s82/I0 |
| 60.035 | 0.526 | tINS | RR | 5 | uart_byte_tx/n57_s82/F |
| 60.410 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s61/I0 |
| 60.936 | 0.526 | tINS | RR | 4 | uart_byte_tx/n57_s61/F |
| 61.311 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s53/I1 |
| 61.827 | 0.516 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 62.202 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 62.719 | 0.516 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 63.094 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 63.620 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 63.995 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 64.521 | 0.526 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 64.896 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 65.422 | 0.526 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 65.797 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 66.324 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 66.699 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 67.225 | 0.526 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 67.600 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 68.126 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 68.501 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 69.028 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 69.403 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 69.929 | 0.526 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 70.304 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 70.820 | 0.516 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 71.195 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 71.721 | 0.526 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 72.096 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s216/I0 |
| 72.623 | 0.526 | tINS | RR | 4 | uart_byte_tx/n60_s216/F |
| 72.998 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s63/I1 |
| 73.514 | 0.516 | tINS | RR | 4 | uart_byte_tx/n60_s63/F |
| 73.889 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s49/I1 |
| 74.405 | 0.516 | tINS | RR | 3 | uart_byte_tx/n60_s49/F |
| 74.780 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s45/I0 |
| 75.306 | 0.526 | tINS | RR | 2 | uart_byte_tx/n60_s45/F |
| 75.681 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s395/I0 |
| 76.208 | 0.526 | tINS | RR | 8 | uart_byte_tx/n61_s395/F |
| 76.583 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s392/I0 |
| 77.109 | 0.526 | tINS | RR | 1 | uart_byte_tx/n61_s392/F |
| 77.484 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s358/I1 |
| 78.000 | 0.516 | tINS | RR | 1 | uart_byte_tx/n61_s358/F |
| 78.375 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s334/I0 |
| 78.901 | 0.526 | tINS | RR | 1 | uart_byte_tx/n61_s334/F |
| 79.276 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s322/I0 |
| 79.803 | 0.526 | tINS | RR | 1 | uart_byte_tx/n61_s322/F |
| 80.178 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s318/I0 |
| 80.704 | 0.526 | tINS | RR | 1 | uart_byte_tx/n61_s318/F |
| 81.079 | 0.375 | tNET | RR | 1 | uart_byte_tx/n61_s317/I0 |
| 81.605 | 0.526 | tINS | RR | 1 | uart_byte_tx/n61_s317/F |
| 81.980 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_0_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 91 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 47.097, 57.714%; route: 34.125, 41.817%; tC2Q: 0.382, 0.469% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -66.271 |
| Data Arrival Time | 76.583 |
| Data Required Time | 10.311 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_1_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.034 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.560 | 0.526 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 2.935 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.461 | 0.526 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 3.836 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.362 | 0.526 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 4.737 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.264 | 0.526 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 5.639 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.100 | 0.461 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 6.475 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 6.991 | 0.516 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 7.366 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 7.892 | 0.526 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 8.267 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 8.784 | 0.516 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 9.159 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 9.675 | 0.516 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 10.050 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 10.576 | 0.526 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 10.951 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 11.477 | 0.526 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 11.852 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 12.379 | 0.526 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 12.754 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 13.280 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 13.655 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 14.181 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 14.556 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 15.082 | 0.526 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 15.457 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 15.984 | 0.526 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 16.359 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 16.875 | 0.516 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 17.250 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 17.776 | 0.526 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 18.151 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 18.678 | 0.526 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 19.053 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 19.579 | 0.526 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 19.954 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 20.470 | 0.516 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 20.845 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 21.371 | 0.526 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 21.746 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 22.273 | 0.526 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 22.648 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 23.174 | 0.526 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 23.549 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 24.075 | 0.526 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 24.450 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 24.976 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 25.351 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 25.878 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 26.253 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 26.779 | 0.526 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 27.154 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 27.680 | 0.526 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 28.055 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 28.571 | 0.516 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 28.946 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 29.473 | 0.526 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 29.848 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 30.374 | 0.526 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 30.749 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 31.275 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 31.650 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 32.176 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 32.551 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 33.078 | 0.526 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 33.453 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 33.979 | 0.526 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 34.354 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 34.880 | 0.526 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 35.255 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 35.771 | 0.516 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 36.146 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 36.673 | 0.526 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 37.048 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 37.564 | 0.516 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 37.939 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 38.455 | 0.516 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 38.830 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 39.346 | 0.516 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 39.721 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 40.248 | 0.526 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 40.623 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 41.149 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 41.524 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 42.050 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 42.425 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 42.951 | 0.526 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 43.326 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 43.853 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 44.228 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 44.754 | 0.526 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 45.129 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 45.645 | 0.516 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 46.020 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 46.546 | 0.526 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 46.921 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 47.448 | 0.526 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 47.823 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 48.349 | 0.526 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 48.724 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 49.250 | 0.526 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 49.625 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 50.151 | 0.526 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 50.526 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 51.052 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 51.427 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 51.954 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 52.329 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 52.845 | 0.516 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 53.220 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 53.736 | 0.516 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 54.111 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s77/I0 |
| 54.637 | 0.526 | tINS | RR | 5 | uart_byte_tx/n56_s77/F |
| 55.012 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s45/I1 |
| 55.529 | 0.516 | tINS | RR | 3 | uart_byte_tx/n56_s45/F |
| 55.904 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s29/I0 |
| 56.430 | 0.526 | tINS | RR | 2 | uart_byte_tx/n56_s29/F |
| 56.805 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s23/I0 |
| 57.331 | 0.526 | tINS | RR | 4 | uart_byte_tx/n56_s23/F |
| 57.706 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s21/I0 |
| 58.232 | 0.526 | tINS | RR | 14 | uart_byte_tx/n56_s21/F |
| 58.607 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n31_s52/I0 |
| 59.134 | 0.526 | tINS | RR | 22 | Spi_Master_Ctrl/n31_s52/F |
| 59.509 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s82/I0 |
| 60.035 | 0.526 | tINS | RR | 5 | uart_byte_tx/n57_s82/F |
| 60.410 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s61/I0 |
| 60.936 | 0.526 | tINS | RR | 4 | uart_byte_tx/n57_s61/F |
| 61.311 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s53/I1 |
| 61.827 | 0.516 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 62.202 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 62.719 | 0.516 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 63.094 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 63.620 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 63.995 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 64.521 | 0.526 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 64.896 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 65.422 | 0.526 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 65.797 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 66.324 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 66.699 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 67.225 | 0.526 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 67.600 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 68.126 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 68.501 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 69.028 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 69.403 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 69.929 | 0.526 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 70.304 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 70.820 | 0.516 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 71.195 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 71.721 | 0.526 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 72.096 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s105/I0 |
| 72.623 | 0.526 | tINS | RR | 7 | uart_byte_tx/n60_s105/F |
| 72.998 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s74/I0 |
| 73.524 | 0.526 | tINS | RR | 2 | uart_byte_tx/n60_s74/F |
| 73.899 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s54/I0 |
| 74.425 | 0.526 | tINS | RR | 2 | uart_byte_tx/n60_s54/F |
| 74.800 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s46/I1 |
| 75.316 | 0.516 | tINS | RR | 1 | uart_byte_tx/n60_s46/F |
| 75.691 | 0.375 | tNET | RR | 1 | uart_byte_tx/n60_s44/I1 |
| 76.208 | 0.516 | tINS | RR | 23 | uart_byte_tx/n60_s44/F |
| 76.583 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_1_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 85 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 43.950, 57.671%; route: 31.875, 41.827%; tC2Q: 0.382, 0.502% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | -62.686 |
| Data Arrival Time | 72.997 |
| Data Required Time | 10.311 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | Spi_Master_Ctrl/clk_div_max_1_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.034 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.560 | 0.526 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 2.935 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.461 | 0.526 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 3.836 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.362 | 0.526 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 4.737 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.264 | 0.526 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 5.639 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.100 | 0.461 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 6.475 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 6.991 | 0.516 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 7.366 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 7.892 | 0.526 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 8.267 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 8.784 | 0.516 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 9.159 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 9.675 | 0.516 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 10.050 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 10.576 | 0.526 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 10.951 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 11.477 | 0.526 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 11.852 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 12.379 | 0.526 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 12.754 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 13.280 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 13.655 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 14.181 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 14.556 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 15.082 | 0.526 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 15.457 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 15.984 | 0.526 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 16.359 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 16.875 | 0.516 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 17.250 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 17.776 | 0.526 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 18.151 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 18.678 | 0.526 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 19.053 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 19.579 | 0.526 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 19.954 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 20.470 | 0.516 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 20.845 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 21.371 | 0.526 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 21.746 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 22.273 | 0.526 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 22.648 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 23.174 | 0.526 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 23.549 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 24.075 | 0.526 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 24.450 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 24.976 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 25.351 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 25.878 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 26.253 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 26.779 | 0.526 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 27.154 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 27.680 | 0.526 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 28.055 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 28.571 | 0.516 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 28.946 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 29.473 | 0.526 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 29.848 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 30.374 | 0.526 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 30.749 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 31.275 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 31.650 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 32.176 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 32.551 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 33.078 | 0.526 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 33.453 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 33.979 | 0.526 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 34.354 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 34.880 | 0.526 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 35.255 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 35.771 | 0.516 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 36.146 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 36.673 | 0.526 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 37.048 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 37.564 | 0.516 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 37.939 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 38.455 | 0.516 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 38.830 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 39.346 | 0.516 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 39.721 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 40.248 | 0.526 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 40.623 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 41.149 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 41.524 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 42.050 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 42.425 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 42.951 | 0.526 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 43.326 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 43.853 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 44.228 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 44.754 | 0.526 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 45.129 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 45.645 | 0.516 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 46.020 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 46.546 | 0.526 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 46.921 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 47.448 | 0.526 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 47.823 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 48.349 | 0.526 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 48.724 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 49.250 | 0.526 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 49.625 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 50.151 | 0.526 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 50.526 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 51.052 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 51.427 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 51.954 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 52.329 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 52.845 | 0.516 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 53.220 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 53.736 | 0.516 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 54.111 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s77/I0 |
| 54.637 | 0.526 | tINS | RR | 5 | uart_byte_tx/n56_s77/F |
| 55.012 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s45/I1 |
| 55.529 | 0.516 | tINS | RR | 3 | uart_byte_tx/n56_s45/F |
| 55.904 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s29/I0 |
| 56.430 | 0.526 | tINS | RR | 2 | uart_byte_tx/n56_s29/F |
| 56.805 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s23/I0 |
| 57.331 | 0.526 | tINS | RR | 4 | uart_byte_tx/n56_s23/F |
| 57.706 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s21/I0 |
| 58.232 | 0.526 | tINS | RR | 14 | uart_byte_tx/n56_s21/F |
| 58.607 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n31_s52/I0 |
| 59.134 | 0.526 | tINS | RR | 22 | Spi_Master_Ctrl/n31_s52/F |
| 59.509 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s82/I0 |
| 60.035 | 0.526 | tINS | RR | 5 | uart_byte_tx/n57_s82/F |
| 60.410 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s61/I0 |
| 60.936 | 0.526 | tINS | RR | 4 | uart_byte_tx/n57_s61/F |
| 61.311 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s53/I1 |
| 61.827 | 0.516 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 62.202 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 62.719 | 0.516 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 63.094 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 63.620 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 63.995 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 64.521 | 0.526 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 64.896 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 65.422 | 0.526 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 65.797 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 66.324 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 66.699 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 67.225 | 0.526 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 67.600 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 68.126 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 68.501 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 69.028 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 69.403 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 69.929 | 0.526 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 70.304 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 70.820 | 0.516 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 71.195 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 71.721 | 0.526 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 72.096 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s48/I0 |
| 72.623 | 0.526 | tINS | RR | 19 | uart_byte_tx/n59_s48/F |
| 72.998 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/clk_div_max_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/clk_div_max_1_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | Spi_Master_Ctrl/clk_div_max_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 81 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 41.865, 57.647%; route: 30.375, 41.826%; tC2Q: 0.382, 0.527% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | -62.686 |
| Data Arrival Time | 72.997 |
| Data Required Time | 10.311 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_2_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.034 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.560 | 0.526 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 2.935 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.461 | 0.526 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 3.836 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.362 | 0.526 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 4.737 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.264 | 0.526 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 5.639 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.100 | 0.461 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 6.475 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 6.991 | 0.516 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 7.366 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 7.892 | 0.526 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 8.267 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 8.784 | 0.516 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 9.159 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 9.675 | 0.516 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 10.050 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 10.576 | 0.526 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 10.951 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 11.477 | 0.526 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 11.852 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 12.379 | 0.526 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 12.754 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 13.280 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 13.655 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 14.181 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 14.556 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 15.082 | 0.526 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 15.457 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 15.984 | 0.526 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 16.359 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 16.875 | 0.516 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 17.250 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 17.776 | 0.526 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 18.151 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 18.678 | 0.526 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 19.053 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 19.579 | 0.526 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 19.954 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 20.470 | 0.516 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 20.845 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 21.371 | 0.526 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 21.746 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 22.273 | 0.526 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 22.648 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 23.174 | 0.526 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 23.549 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 24.075 | 0.526 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 24.450 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 24.976 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 25.351 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 25.878 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 26.253 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 26.779 | 0.526 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 27.154 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 27.680 | 0.526 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 28.055 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 28.571 | 0.516 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 28.946 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 29.473 | 0.526 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 29.848 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 30.374 | 0.526 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 30.749 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 31.275 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 31.650 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 32.176 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 32.551 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 33.078 | 0.526 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 33.453 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 33.979 | 0.526 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 34.354 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 34.880 | 0.526 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 35.255 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 35.771 | 0.516 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 36.146 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 36.673 | 0.526 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 37.048 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 37.564 | 0.516 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 37.939 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 38.455 | 0.516 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 38.830 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 39.346 | 0.516 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 39.721 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 40.248 | 0.526 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 40.623 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 41.149 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 41.524 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 42.050 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 42.425 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 42.951 | 0.526 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 43.326 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 43.853 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 44.228 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 44.754 | 0.526 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 45.129 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 45.645 | 0.516 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 46.020 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 46.546 | 0.526 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 46.921 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 47.448 | 0.526 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 47.823 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 48.349 | 0.526 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 48.724 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 49.250 | 0.526 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 49.625 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 50.151 | 0.526 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 50.526 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 51.052 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 51.427 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 51.954 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 52.329 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 52.845 | 0.516 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 53.220 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 53.736 | 0.516 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 54.111 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s77/I0 |
| 54.637 | 0.526 | tINS | RR | 5 | uart_byte_tx/n56_s77/F |
| 55.012 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s45/I1 |
| 55.529 | 0.516 | tINS | RR | 3 | uart_byte_tx/n56_s45/F |
| 55.904 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s29/I0 |
| 56.430 | 0.526 | tINS | RR | 2 | uart_byte_tx/n56_s29/F |
| 56.805 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s23/I0 |
| 57.331 | 0.526 | tINS | RR | 4 | uart_byte_tx/n56_s23/F |
| 57.706 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s21/I0 |
| 58.232 | 0.526 | tINS | RR | 14 | uart_byte_tx/n56_s21/F |
| 58.607 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n31_s52/I0 |
| 59.134 | 0.526 | tINS | RR | 22 | Spi_Master_Ctrl/n31_s52/F |
| 59.509 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s82/I0 |
| 60.035 | 0.526 | tINS | RR | 5 | uart_byte_tx/n57_s82/F |
| 60.410 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s61/I0 |
| 60.936 | 0.526 | tINS | RR | 4 | uart_byte_tx/n57_s61/F |
| 61.311 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s53/I1 |
| 61.827 | 0.516 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 62.202 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 62.719 | 0.516 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 63.094 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 63.620 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 63.995 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 64.521 | 0.526 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 64.896 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 65.422 | 0.526 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 65.797 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 66.324 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 66.699 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 67.225 | 0.526 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 67.600 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 68.126 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 68.501 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 69.028 | 0.526 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 69.403 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 69.929 | 0.526 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 70.304 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 70.820 | 0.516 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 71.195 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 71.721 | 0.526 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 72.096 | 0.375 | tNET | RR | 1 | uart_byte_tx/n59_s48/I0 |
| 72.623 | 0.526 | tINS | RR | 19 | uart_byte_tx/n59_s48/F |
| 72.998 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_2_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 81 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 41.865, 57.647%; route: 30.375, 41.826%; tC2Q: 0.382, 0.527% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | -57.279 |
| Data Arrival Time | 67.590 |
| Data Required Time | 10.311 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_3_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.034 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.560 | 0.526 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 2.935 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.461 | 0.526 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 3.836 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.362 | 0.526 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 4.737 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.264 | 0.526 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 5.639 | 0.375 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.100 | 0.461 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 6.475 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 6.991 | 0.516 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 7.366 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 7.892 | 0.526 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 8.267 | 0.375 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 8.784 | 0.516 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 9.159 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 9.675 | 0.516 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 10.050 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 10.576 | 0.526 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 10.951 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 11.477 | 0.526 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 11.852 | 0.375 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 12.379 | 0.526 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 12.754 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 13.280 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 13.655 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 14.181 | 0.526 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 14.556 | 0.375 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 15.082 | 0.526 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 15.457 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 15.984 | 0.526 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 16.359 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 16.875 | 0.516 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 17.250 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 17.776 | 0.526 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 18.151 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 18.678 | 0.526 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 19.053 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 19.579 | 0.526 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 19.954 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 20.470 | 0.516 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 20.845 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 21.371 | 0.526 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 21.746 | 0.375 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 22.273 | 0.526 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 22.648 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 23.174 | 0.526 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 23.549 | 0.375 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 24.075 | 0.526 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 24.450 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 24.976 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 25.351 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 25.878 | 0.526 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 26.253 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 26.779 | 0.526 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 27.154 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 27.680 | 0.526 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 28.055 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 28.571 | 0.516 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 28.946 | 0.375 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 29.473 | 0.526 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 29.848 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 30.374 | 0.526 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 30.749 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 31.275 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 31.650 | 0.375 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 32.176 | 0.526 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 32.551 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 33.078 | 0.526 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 33.453 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 33.979 | 0.526 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 34.354 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 34.880 | 0.526 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 35.255 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 35.771 | 0.516 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 36.146 | 0.375 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 36.673 | 0.526 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 37.048 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 37.564 | 0.516 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 37.939 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 38.455 | 0.516 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 38.830 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 39.346 | 0.516 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 39.721 | 0.375 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 40.248 | 0.526 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 40.623 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 41.149 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 41.524 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 42.050 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 42.425 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 42.951 | 0.526 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 43.326 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 43.853 | 0.526 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 44.228 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 44.754 | 0.526 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 45.129 | 0.375 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 45.645 | 0.516 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 46.020 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 46.546 | 0.526 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 46.921 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 47.448 | 0.526 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 47.823 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 48.349 | 0.526 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 48.724 | 0.375 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 49.250 | 0.526 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 49.625 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 50.151 | 0.526 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 50.526 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 51.052 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 51.427 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 51.954 | 0.526 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 52.329 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 52.845 | 0.516 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 53.220 | 0.375 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 53.736 | 0.516 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 54.111 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s77/I0 |
| 54.637 | 0.526 | tINS | RR | 5 | uart_byte_tx/n56_s77/F |
| 55.012 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s45/I1 |
| 55.529 | 0.516 | tINS | RR | 3 | uart_byte_tx/n56_s45/F |
| 55.904 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s29/I0 |
| 56.430 | 0.526 | tINS | RR | 2 | uart_byte_tx/n56_s29/F |
| 56.805 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s23/I0 |
| 57.331 | 0.526 | tINS | RR | 4 | uart_byte_tx/n56_s23/F |
| 57.706 | 0.375 | tNET | RR | 1 | uart_byte_tx/n56_s21/I0 |
| 58.232 | 0.526 | tINS | RR | 14 | uart_byte_tx/n56_s21/F |
| 58.607 | 0.375 | tNET | RR | 1 | Spi_Master_Ctrl/n31_s52/I0 |
| 59.134 | 0.526 | tINS | RR | 22 | Spi_Master_Ctrl/n31_s52/F |
| 59.509 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s82/I0 |
| 60.035 | 0.526 | tINS | RR | 5 | uart_byte_tx/n57_s82/F |
| 60.410 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s61/I0 |
| 60.936 | 0.526 | tINS | RR | 4 | uart_byte_tx/n57_s61/F |
| 61.311 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s53/I1 |
| 61.827 | 0.516 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 62.202 | 0.375 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 62.719 | 0.516 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 63.094 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 63.620 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 63.995 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 64.521 | 0.526 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 64.896 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 65.422 | 0.526 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 65.797 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 66.324 | 0.526 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 66.699 | 0.375 | tNET | RR | 1 | uart_byte_tx/n58_s50/I1 |
| 67.215 | 0.516 | tINS | RR | 23 | uart_byte_tx/n58_s50/F |
| 67.590 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | uart_byte_tx/bps_DR_3_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 75 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 38.708, 57.588%; route: 28.125, 41.843%; tC2Q: 0.382, 0.569% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |