Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\FX2_CDC_UART_SPI.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\SPI_Slave.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\Spi_Master_Ctrl.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\User_Param.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\byte_tx_control.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\fifo_1024x8.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\fx2_fifo_crtl.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\hc595_driver.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\hex8.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\uart_byte_rx.v C:\Users\24165\Desktop\60k_FX2_CDC_UART_SPI\FX2_CDC_UART_SPI\src\uart_byte_tx.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Tue Aug 5 11:40:30 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FX2_CDC_UART_SPI |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.689s, Peak memory usage = 261.707MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 261.707MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.137s, Peak memory usage = 261.707MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.332s, Peak memory usage = 261.707MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 261.707MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 261.707MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 261.707MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 261.707MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 261.707MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 261.707MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 261.707MB Tech-Mapping Phase 3: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s, Peak memory usage = 275.457MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.237s, Peak memory usage = 275.457MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 275.457MB |
| Total Time and Memory Usage | CPU time = 0h 0m 19s, Elapsed time = 0h 0m 19s, Peak memory usage = 275.457MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 35 |
| I/O Buf | 35 |
| IBUF | 12 |
| OBUF | 14 |
| TBUF | 1 |
| IOBUF | 8 |
| Register | 976 |
| DFFRE | 457 |
| DFFPE | 21 |
| DFFCE | 498 |
| LUT | 2959 |
| LUT2 | 324 |
| LUT3 | 885 |
| LUT4 | 1750 |
| ALU | 84 |
| ALU | 84 |
| INV | 8 |
| INV | 8 |
| BSRAM | 2 |
| SDPB | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3051(2967 LUT, 84 ALU) / 138240 | 3% |
| Register | 976 / 139095 | <1% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 976 / 139095 | <1% |
| BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | FX2_SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_SPI_SCLK_ibuf/I | ||
| 4 | hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | hex8/clk_1K_s1/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.000(MHz) | 135.777(MHz) | 8 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 11.139(MHz) | 91 | TOP |
| 3 | FX2_SPI_SCLK | 100.000(MHz) | 266.934(MHz) | 4 | TOP |
| 4 | hex8/clk_1K | 100.000(MHz) | 361.011(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -79.775 |
| Data Arrival Time | 90.124 |
| Data Required Time | 10.349 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_0_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.199 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.778 | 0.579 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 3.190 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.769 | 0.579 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 4.181 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 5.173 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.751 | 0.579 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 6.164 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.671 | 0.507 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 7.084 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 7.651 | 0.567 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 8.064 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 8.642 | 0.579 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 9.055 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 9.623 | 0.567 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 10.035 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 10.603 | 0.567 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 11.015 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 11.594 | 0.579 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 12.006 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 12.585 | 0.579 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 12.998 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 13.576 | 0.579 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 13.989 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 14.568 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 14.980 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 15.559 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 15.971 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 16.550 | 0.579 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 16.963 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 17.541 | 0.579 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 17.954 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 18.521 | 0.567 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 18.934 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 19.513 | 0.579 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 19.925 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 20.504 | 0.579 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 20.916 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 21.495 | 0.579 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 21.908 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 22.475 | 0.567 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 22.888 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 23.466 | 0.579 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 23.879 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 24.458 | 0.579 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 24.870 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 25.449 | 0.579 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 25.861 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 26.440 | 0.579 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 26.853 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 27.431 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 27.844 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 28.423 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 28.835 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 29.414 | 0.579 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 29.826 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 30.405 | 0.579 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 30.818 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 31.385 | 0.567 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 31.798 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 32.376 | 0.579 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 32.789 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 33.368 | 0.579 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 33.780 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 34.359 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 34.771 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 35.350 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 35.763 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 36.341 | 0.579 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 36.754 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 37.333 | 0.579 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 37.745 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 38.324 | 0.579 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 38.736 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 39.304 | 0.567 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 39.716 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 40.295 | 0.579 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 40.708 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 41.275 | 0.567 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 41.688 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 42.255 | 0.567 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 42.668 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 43.235 | 0.567 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 43.648 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 44.226 | 0.579 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 44.639 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 45.218 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 45.630 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 46.209 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 46.621 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 47.200 | 0.579 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 47.612 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 48.191 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 48.604 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 49.182 | 0.579 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 49.595 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 50.162 | 0.567 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 50.575 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 51.154 | 0.579 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 51.566 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 52.145 | 0.579 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 52.557 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 53.136 | 0.579 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 53.549 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 54.127 | 0.579 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 54.540 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 55.119 | 0.579 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 55.531 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 56.110 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 56.522 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 57.101 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 57.514 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 58.081 | 0.567 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 58.494 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 59.061 | 0.567 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 59.474 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s83/I0 |
| 60.052 | 0.579 | tINS | RR | 1 | uart_byte_tx/n56_s83/F |
| 60.465 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s52/I1 |
| 61.032 | 0.567 | tINS | RR | 5 | uart_byte_tx/n56_s52/F |
| 61.445 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s32/I0 |
| 62.024 | 0.579 | tINS | RR | 6 | uart_byte_tx/n56_s32/F |
| 62.436 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s175/I0 |
| 63.015 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s175/F |
| 63.427 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s152/I1 |
| 63.995 | 0.567 | tINS | RR | 1 | uart_byte_tx/n57_s152/F |
| 64.407 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s113/I0 |
| 64.986 | 0.579 | tINS | RR | 5 | uart_byte_tx/n57_s113/F |
| 65.399 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s80/I0 |
| 65.977 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s80/F |
| 66.390 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s60/I0 |
| 66.969 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s60/F |
| 67.381 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s53/I0 |
| 67.960 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 68.372 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 68.940 | 0.567 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 69.352 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 69.931 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 70.344 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 70.922 | 0.579 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 71.335 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 71.914 | 0.579 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 72.326 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 72.905 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 73.317 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 73.896 | 0.579 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 74.309 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 74.887 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 75.300 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 75.879 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 76.291 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 76.870 | 0.579 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 77.282 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 77.850 | 0.567 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 78.262 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 78.841 | 0.579 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 79.254 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s216/I0 |
| 79.832 | 0.579 | tINS | RR | 4 | uart_byte_tx/n60_s216/F |
| 80.245 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s63/I1 |
| 80.812 | 0.567 | tINS | RR | 4 | uart_byte_tx/n60_s63/F |
| 81.225 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s49/I1 |
| 81.792 | 0.567 | tINS | RR | 3 | uart_byte_tx/n60_s49/F |
| 82.205 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s45/I0 |
| 82.784 | 0.579 | tINS | RR | 2 | uart_byte_tx/n60_s45/F |
| 83.196 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s395/I0 |
| 83.775 | 0.579 | tINS | RR | 8 | uart_byte_tx/n61_s395/F |
| 84.187 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s392/I0 |
| 84.766 | 0.579 | tINS | RR | 1 | uart_byte_tx/n61_s392/F |
| 85.179 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s358/I1 |
| 85.746 | 0.567 | tINS | RR | 1 | uart_byte_tx/n61_s358/F |
| 86.159 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s334/I0 |
| 86.737 | 0.579 | tINS | RR | 1 | uart_byte_tx/n61_s334/F |
| 87.150 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s322/I0 |
| 87.729 | 0.579 | tINS | RR | 1 | uart_byte_tx/n61_s322/F |
| 88.141 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s318/I0 |
| 88.720 | 0.579 | tINS | RR | 1 | uart_byte_tx/n61_s318/F |
| 89.132 | 0.413 | tNET | RR | 1 | uart_byte_tx/n61_s317/I0 |
| 89.711 | 0.579 | tINS | RR | 1 | uart_byte_tx/n61_s317/F |
| 90.124 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_0_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 91 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 51.791, 57.731%; route: 37.537, 41.843%; tC2Q: 0.382, 0.426% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | -73.839 |
| Data Arrival Time | 84.187 |
| Data Required Time | 10.349 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_1_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.199 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.778 | 0.579 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 3.190 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.769 | 0.579 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 4.181 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 5.173 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.751 | 0.579 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 6.164 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.671 | 0.507 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 7.084 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 7.651 | 0.567 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 8.064 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 8.642 | 0.579 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 9.055 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 9.623 | 0.567 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 10.035 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 10.603 | 0.567 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 11.015 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 11.594 | 0.579 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 12.006 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 12.585 | 0.579 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 12.998 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 13.576 | 0.579 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 13.989 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 14.568 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 14.980 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 15.559 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 15.971 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 16.550 | 0.579 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 16.963 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 17.541 | 0.579 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 17.954 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 18.521 | 0.567 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 18.934 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 19.513 | 0.579 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 19.925 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 20.504 | 0.579 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 20.916 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 21.495 | 0.579 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 21.908 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 22.475 | 0.567 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 22.888 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 23.466 | 0.579 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 23.879 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 24.458 | 0.579 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 24.870 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 25.449 | 0.579 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 25.861 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 26.440 | 0.579 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 26.853 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 27.431 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 27.844 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 28.423 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 28.835 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 29.414 | 0.579 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 29.826 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 30.405 | 0.579 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 30.818 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 31.385 | 0.567 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 31.798 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 32.376 | 0.579 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 32.789 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 33.368 | 0.579 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 33.780 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 34.359 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 34.771 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 35.350 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 35.763 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 36.341 | 0.579 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 36.754 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 37.333 | 0.579 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 37.745 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 38.324 | 0.579 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 38.736 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 39.304 | 0.567 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 39.716 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 40.295 | 0.579 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 40.708 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 41.275 | 0.567 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 41.688 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 42.255 | 0.567 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 42.668 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 43.235 | 0.567 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 43.648 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 44.226 | 0.579 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 44.639 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 45.218 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 45.630 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 46.209 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 46.621 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 47.200 | 0.579 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 47.612 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 48.191 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 48.604 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 49.182 | 0.579 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 49.595 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 50.162 | 0.567 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 50.575 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 51.154 | 0.579 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 51.566 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 52.145 | 0.579 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 52.557 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 53.136 | 0.579 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 53.549 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 54.127 | 0.579 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 54.540 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 55.119 | 0.579 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 55.531 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 56.110 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 56.522 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 57.101 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 57.514 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 58.081 | 0.567 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 58.494 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 59.061 | 0.567 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 59.474 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s83/I0 |
| 60.052 | 0.579 | tINS | RR | 1 | uart_byte_tx/n56_s83/F |
| 60.465 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s52/I1 |
| 61.032 | 0.567 | tINS | RR | 5 | uart_byte_tx/n56_s52/F |
| 61.445 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s32/I0 |
| 62.024 | 0.579 | tINS | RR | 6 | uart_byte_tx/n56_s32/F |
| 62.436 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s175/I0 |
| 63.015 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s175/F |
| 63.427 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s152/I1 |
| 63.995 | 0.567 | tINS | RR | 1 | uart_byte_tx/n57_s152/F |
| 64.407 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s113/I0 |
| 64.986 | 0.579 | tINS | RR | 5 | uart_byte_tx/n57_s113/F |
| 65.399 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s80/I0 |
| 65.977 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s80/F |
| 66.390 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s60/I0 |
| 66.969 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s60/F |
| 67.381 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s53/I0 |
| 67.960 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 68.372 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 68.940 | 0.567 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 69.352 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 69.931 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 70.344 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 70.922 | 0.579 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 71.335 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 71.914 | 0.579 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 72.326 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 72.905 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 73.317 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 73.896 | 0.579 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 74.309 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 74.887 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 75.300 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 75.879 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 76.291 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 76.870 | 0.579 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 77.282 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 77.850 | 0.567 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 78.262 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 78.841 | 0.579 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 79.254 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s105/I0 |
| 79.832 | 0.579 | tINS | RR | 7 | uart_byte_tx/n60_s105/F |
| 80.245 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s74/I0 |
| 80.824 | 0.579 | tINS | RR | 2 | uart_byte_tx/n60_s74/F |
| 81.236 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s54/I0 |
| 81.815 | 0.579 | tINS | RR | 2 | uart_byte_tx/n60_s54/F |
| 82.227 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s46/I1 |
| 82.795 | 0.567 | tINS | RR | 1 | uart_byte_tx/n60_s46/F |
| 83.207 | 0.413 | tNET | RR | 1 | uart_byte_tx/n60_s44/I1 |
| 83.775 | 0.567 | tINS | RR | 23 | uart_byte_tx/n60_s44/F |
| 84.187 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_1_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 85 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 48.330, 57.690%; route: 35.063, 41.853%; tC2Q: 0.382, 0.457% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | -69.896 |
| Data Arrival Time | 80.245 |
| Data Required Time | 10.349 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | Spi_Master_Ctrl/clk_div_max_1_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.199 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.778 | 0.579 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 3.190 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.769 | 0.579 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 4.181 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 5.173 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.751 | 0.579 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 6.164 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.671 | 0.507 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 7.084 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 7.651 | 0.567 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 8.064 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 8.642 | 0.579 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 9.055 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 9.623 | 0.567 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 10.035 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 10.603 | 0.567 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 11.015 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 11.594 | 0.579 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 12.006 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 12.585 | 0.579 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 12.998 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 13.576 | 0.579 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 13.989 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 14.568 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 14.980 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 15.559 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 15.971 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 16.550 | 0.579 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 16.963 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 17.541 | 0.579 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 17.954 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 18.521 | 0.567 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 18.934 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 19.513 | 0.579 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 19.925 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 20.504 | 0.579 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 20.916 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 21.495 | 0.579 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 21.908 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 22.475 | 0.567 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 22.888 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 23.466 | 0.579 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 23.879 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 24.458 | 0.579 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 24.870 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 25.449 | 0.579 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 25.861 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 26.440 | 0.579 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 26.853 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 27.431 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 27.844 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 28.423 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 28.835 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 29.414 | 0.579 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 29.826 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 30.405 | 0.579 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 30.818 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 31.385 | 0.567 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 31.798 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 32.376 | 0.579 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 32.789 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 33.368 | 0.579 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 33.780 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 34.359 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 34.771 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 35.350 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 35.763 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 36.341 | 0.579 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 36.754 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 37.333 | 0.579 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 37.745 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 38.324 | 0.579 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 38.736 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 39.304 | 0.567 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 39.716 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 40.295 | 0.579 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 40.708 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 41.275 | 0.567 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 41.688 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 42.255 | 0.567 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 42.668 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 43.235 | 0.567 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 43.648 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 44.226 | 0.579 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 44.639 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 45.218 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 45.630 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 46.209 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 46.621 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 47.200 | 0.579 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 47.612 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 48.191 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 48.604 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 49.182 | 0.579 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 49.595 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 50.162 | 0.567 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 50.575 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 51.154 | 0.579 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 51.566 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 52.145 | 0.579 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 52.557 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 53.136 | 0.579 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 53.549 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 54.127 | 0.579 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 54.540 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 55.119 | 0.579 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 55.531 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 56.110 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 56.522 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 57.101 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 57.514 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 58.081 | 0.567 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 58.494 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 59.061 | 0.567 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 59.474 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s83/I0 |
| 60.052 | 0.579 | tINS | RR | 1 | uart_byte_tx/n56_s83/F |
| 60.465 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s52/I1 |
| 61.032 | 0.567 | tINS | RR | 5 | uart_byte_tx/n56_s52/F |
| 61.445 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s32/I0 |
| 62.024 | 0.579 | tINS | RR | 6 | uart_byte_tx/n56_s32/F |
| 62.436 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s175/I0 |
| 63.015 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s175/F |
| 63.427 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s152/I1 |
| 63.995 | 0.567 | tINS | RR | 1 | uart_byte_tx/n57_s152/F |
| 64.407 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s113/I0 |
| 64.986 | 0.579 | tINS | RR | 5 | uart_byte_tx/n57_s113/F |
| 65.399 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s80/I0 |
| 65.977 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s80/F |
| 66.390 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s60/I0 |
| 66.969 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s60/F |
| 67.381 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s53/I0 |
| 67.960 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 68.372 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 68.940 | 0.567 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 69.352 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 69.931 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 70.344 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 70.922 | 0.579 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 71.335 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 71.914 | 0.579 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 72.326 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 72.905 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 73.317 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 73.896 | 0.579 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 74.309 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 74.887 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 75.300 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 75.879 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 76.291 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 76.870 | 0.579 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 77.282 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 77.850 | 0.567 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 78.262 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 78.841 | 0.579 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 79.254 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s48/I0 |
| 79.832 | 0.579 | tINS | RR | 19 | uart_byte_tx/n59_s48/F |
| 80.245 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/clk_div_max_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/clk_div_max_1_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | Spi_Master_Ctrl/clk_div_max_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 81 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 46.038, 57.668%; route: 33.413, 41.853%; tC2Q: 0.382, 0.479% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | -69.896 |
| Data Arrival Time | 80.245 |
| Data Required Time | 10.349 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_2_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.199 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.778 | 0.579 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 3.190 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.769 | 0.579 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 4.181 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 5.173 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.751 | 0.579 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 6.164 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.671 | 0.507 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 7.084 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 7.651 | 0.567 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 8.064 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 8.642 | 0.579 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 9.055 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 9.623 | 0.567 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 10.035 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 10.603 | 0.567 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 11.015 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 11.594 | 0.579 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 12.006 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 12.585 | 0.579 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 12.998 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 13.576 | 0.579 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 13.989 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 14.568 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 14.980 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 15.559 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 15.971 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 16.550 | 0.579 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 16.963 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 17.541 | 0.579 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 17.954 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 18.521 | 0.567 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 18.934 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 19.513 | 0.579 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 19.925 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 20.504 | 0.579 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 20.916 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 21.495 | 0.579 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 21.908 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 22.475 | 0.567 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 22.888 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 23.466 | 0.579 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 23.879 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 24.458 | 0.579 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 24.870 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 25.449 | 0.579 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 25.861 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 26.440 | 0.579 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 26.853 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 27.431 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 27.844 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 28.423 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 28.835 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 29.414 | 0.579 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 29.826 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 30.405 | 0.579 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 30.818 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 31.385 | 0.567 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 31.798 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 32.376 | 0.579 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 32.789 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 33.368 | 0.579 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 33.780 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 34.359 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 34.771 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 35.350 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 35.763 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 36.341 | 0.579 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 36.754 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 37.333 | 0.579 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 37.745 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 38.324 | 0.579 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 38.736 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 39.304 | 0.567 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 39.716 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 40.295 | 0.579 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 40.708 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 41.275 | 0.567 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 41.688 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 42.255 | 0.567 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 42.668 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 43.235 | 0.567 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 43.648 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 44.226 | 0.579 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 44.639 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 45.218 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 45.630 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 46.209 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 46.621 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 47.200 | 0.579 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 47.612 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 48.191 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 48.604 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 49.182 | 0.579 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 49.595 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 50.162 | 0.567 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 50.575 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 51.154 | 0.579 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 51.566 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 52.145 | 0.579 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 52.557 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 53.136 | 0.579 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 53.549 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 54.127 | 0.579 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 54.540 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 55.119 | 0.579 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 55.531 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 56.110 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 56.522 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 57.101 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 57.514 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 58.081 | 0.567 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 58.494 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 59.061 | 0.567 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 59.474 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s83/I0 |
| 60.052 | 0.579 | tINS | RR | 1 | uart_byte_tx/n56_s83/F |
| 60.465 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s52/I1 |
| 61.032 | 0.567 | tINS | RR | 5 | uart_byte_tx/n56_s52/F |
| 61.445 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s32/I0 |
| 62.024 | 0.579 | tINS | RR | 6 | uart_byte_tx/n56_s32/F |
| 62.436 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s175/I0 |
| 63.015 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s175/F |
| 63.427 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s152/I1 |
| 63.995 | 0.567 | tINS | RR | 1 | uart_byte_tx/n57_s152/F |
| 64.407 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s113/I0 |
| 64.986 | 0.579 | tINS | RR | 5 | uart_byte_tx/n57_s113/F |
| 65.399 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s80/I0 |
| 65.977 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s80/F |
| 66.390 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s60/I0 |
| 66.969 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s60/F |
| 67.381 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s53/I0 |
| 67.960 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 68.372 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 68.940 | 0.567 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 69.352 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 69.931 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 70.344 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 70.922 | 0.579 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 71.335 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 71.914 | 0.579 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 72.326 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 72.905 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 73.317 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s106/I0 |
| 73.896 | 0.579 | tINS | RR | 9 | uart_byte_tx/n59_s106/F |
| 74.309 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s103/I0 |
| 74.887 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s103/F |
| 75.300 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s74/I0 |
| 75.879 | 0.579 | tINS | RR | 5 | uart_byte_tx/n59_s74/F |
| 76.291 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s57/I0 |
| 76.870 | 0.579 | tINS | RR | 4 | uart_byte_tx/n59_s57/F |
| 77.282 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s51/I1 |
| 77.850 | 0.567 | tINS | RR | 6 | uart_byte_tx/n59_s51/F |
| 78.262 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s49/I0 |
| 78.841 | 0.579 | tINS | RR | 24 | uart_byte_tx/n59_s49/F |
| 79.254 | 0.413 | tNET | RR | 1 | uart_byte_tx/n59_s48/I0 |
| 79.832 | 0.579 | tINS | RR | 19 | uart_byte_tx/n59_s48/F |
| 80.245 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_2_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 81 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 46.038, 57.668%; route: 33.413, 41.853%; tC2Q: 0.382, 0.479% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | -63.949 |
| Data Arrival Time | 74.297 |
| Data Required Time | 10.349 |
| From | User_Param_inst/Param_Reg[2]_6_s0 |
| To | uart_byte_tx/bps_DR_3_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | User_Param_inst/Param_Reg[2]_6_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 21 | User_Param_inst/Param_Reg[2]_6_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s45/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | Spi_Master_Ctrl/n14_s45/F |
| 2.199 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n14_s42/I0 |
| 2.778 | 0.579 | tINS | RR | 42 | Spi_Master_Ctrl/n14_s42/F |
| 3.190 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n16_s64/I0 |
| 3.769 | 0.579 | tINS | RR | 3 | Spi_Master_Ctrl/n16_s64/F |
| 4.181 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s70/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | uart_byte_rx/n25_s70/F |
| 5.173 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s62/I0 |
| 5.751 | 0.579 | tINS | RR | 4 | uart_byte_rx/n25_s62/F |
| 6.164 | 0.413 | tNET | RR | 1 | uart_byte_rx/n25_s56/I2 |
| 6.671 | 0.507 | tINS | RR | 7 | uart_byte_rx/n25_s56/F |
| 7.084 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s88/I1 |
| 7.651 | 0.567 | tINS | RR | 3 | uart_byte_rx/n26_s88/F |
| 8.064 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s79/I0 |
| 8.642 | 0.579 | tINS | RR | 6 | uart_byte_rx/n26_s79/F |
| 9.055 | 0.413 | tNET | RR | 1 | uart_byte_rx/n26_s74/I1 |
| 9.623 | 0.567 | tINS | RR | 7 | uart_byte_rx/n26_s74/F |
| 10.035 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s64/I1 |
| 10.603 | 0.567 | tINS | RR | 7 | uart_byte_rx/n27_s64/F |
| 11.015 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s54/I0 |
| 11.594 | 0.579 | tINS | RR | 1 | uart_byte_rx/n27_s54/F |
| 12.006 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s50/I0 |
| 12.585 | 0.579 | tINS | RR | 2 | uart_byte_rx/n27_s50/F |
| 12.998 | 0.413 | tNET | RR | 1 | uart_byte_rx/n27_s48/I0 |
| 13.576 | 0.579 | tINS | RR | 12 | uart_byte_rx/n27_s48/F |
| 13.989 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s74/I0 |
| 14.568 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s74/F |
| 14.980 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s67/I0 |
| 15.559 | 0.579 | tINS | RR | 2 | uart_byte_rx/n28_s67/F |
| 15.971 | 0.413 | tNET | RR | 1 | uart_byte_rx/n28_s62/I0 |
| 16.550 | 0.579 | tINS | RR | 10 | uart_byte_rx/n28_s62/F |
| 16.963 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s57/I0 |
| 17.541 | 0.579 | tINS | RR | 5 | Spi_Master_Ctrl/n21_s57/F |
| 17.954 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s45/I1 |
| 18.521 | 0.567 | tINS | RR | 3 | Spi_Master_Ctrl/n21_s45/F |
| 18.934 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s41/I0 |
| 19.513 | 0.579 | tINS | RR | 4 | Spi_Master_Ctrl/n21_s41/F |
| 19.925 | 0.413 | tNET | RR | 1 | Spi_Master_Ctrl/n21_s40/I0 |
| 20.504 | 0.579 | tINS | RR | 27 | Spi_Master_Ctrl/n21_s40/F |
| 20.916 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s69/I0 |
| 21.495 | 0.579 | tINS | RR | 3 | uart_byte_tx/n47_s69/F |
| 21.908 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s61/I1 |
| 22.475 | 0.567 | tINS | RR | 6 | uart_byte_tx/n47_s61/F |
| 22.888 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s58/I0 |
| 23.466 | 0.579 | tINS | RR | 12 | uart_byte_tx/n47_s58/F |
| 23.879 | 0.413 | tNET | RR | 1 | uart_byte_tx/n47_s57/I0 |
| 24.458 | 0.579 | tINS | RR | 22 | uart_byte_tx/n47_s57/F |
| 24.870 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s38/I0 |
| 25.449 | 0.579 | tINS | RR | 2 | uart_byte_tx/n48_s38/F |
| 25.861 | 0.413 | tNET | RR | 1 | uart_byte_tx/n48_s96/I0 |
| 26.440 | 0.579 | tINS | RR | 4 | uart_byte_tx/n48_s96/F |
| 26.853 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s160/I0 |
| 27.431 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s160/F |
| 27.844 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s140/I0 |
| 28.423 | 0.579 | tINS | RR | 3 | uart_byte_tx/n49_s140/F |
| 28.835 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s120/I0 |
| 29.414 | 0.579 | tINS | RR | 1 | uart_byte_tx/n49_s120/F |
| 29.826 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s107/I0 |
| 30.405 | 0.579 | tINS | RR | 5 | uart_byte_tx/n49_s107/F |
| 30.818 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s102/I1 |
| 31.385 | 0.567 | tINS | RR | 6 | uart_byte_tx/n49_s102/F |
| 31.798 | 0.413 | tNET | RR | 1 | uart_byte_tx/n49_s101/I0 |
| 32.376 | 0.579 | tINS | RR | 36 | uart_byte_tx/n49_s101/F |
| 32.789 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s115/I0 |
| 33.368 | 0.579 | tINS | RR | 5 | uart_byte_tx/n50_s115/F |
| 33.780 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s97/I0 |
| 34.359 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s97/F |
| 34.771 | 0.413 | tNET | RR | 1 | uart_byte_tx/n50_s90/I0 |
| 35.350 | 0.579 | tINS | RR | 3 | uart_byte_tx/n50_s90/F |
| 35.763 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s99/I0 |
| 36.341 | 0.579 | tINS | RR | 12 | uart_byte_tx/n52_s99/F |
| 36.754 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s190/I0 |
| 37.333 | 0.579 | tINS | RR | 4 | uart_byte_tx/n52_s190/F |
| 37.745 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s100/I0 |
| 38.324 | 0.579 | tINS | RR | 3 | uart_byte_tx/n51_s100/F |
| 38.736 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s91/I1 |
| 39.304 | 0.567 | tINS | RR | 6 | uart_byte_tx/n51_s91/F |
| 39.716 | 0.413 | tNET | RR | 1 | uart_byte_tx/n51_s89/I0 |
| 40.295 | 0.579 | tINS | RR | 15 | uart_byte_tx/n51_s89/F |
| 40.708 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s114/I1 |
| 41.275 | 0.567 | tINS | RR | 2 | uart_byte_tx/n52_s114/F |
| 41.688 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s85/I1 |
| 42.255 | 0.567 | tINS | RR | 3 | uart_byte_tx/n52_s85/F |
| 42.668 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s160/I1 |
| 43.235 | 0.567 | tINS | RR | 3 | uart_byte_tx/n53_s160/F |
| 43.648 | 0.413 | tNET | RR | 1 | uart_byte_tx/n52_s61/I0 |
| 44.226 | 0.579 | tINS | RR | 3 | uart_byte_tx/n52_s61/F |
| 44.639 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s135/I0 |
| 45.218 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s135/F |
| 45.630 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s112/I0 |
| 46.209 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s112/F |
| 46.621 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s90/I0 |
| 47.200 | 0.579 | tINS | RR | 1 | uart_byte_tx/n53_s90/F |
| 47.612 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s73/I0 |
| 48.191 | 0.579 | tINS | RR | 6 | uart_byte_tx/n53_s73/F |
| 48.604 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s66/I0 |
| 49.182 | 0.579 | tINS | RR | 2 | uart_byte_tx/n53_s66/F |
| 49.595 | 0.413 | tNET | RR | 1 | uart_byte_tx/n53_s64/I1 |
| 50.162 | 0.567 | tINS | RR | 36 | uart_byte_tx/n53_s64/F |
| 50.575 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s96/I0 |
| 51.154 | 0.579 | tINS | RR | 7 | uart_byte_tx/n54_s96/F |
| 51.566 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s73/I0 |
| 52.145 | 0.579 | tINS | RR | 2 | uart_byte_tx/n54_s73/F |
| 52.557 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s61/I0 |
| 53.136 | 0.579 | tINS | RR | 3 | uart_byte_tx/n54_s61/F |
| 53.549 | 0.413 | tNET | RR | 1 | uart_byte_tx/n54_s57/I0 |
| 54.127 | 0.579 | tINS | RR | 13 | uart_byte_tx/n54_s57/F |
| 54.540 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s137/I0 |
| 55.119 | 0.579 | tINS | RR | 4 | uart_byte_tx/n55_s137/F |
| 55.531 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s93/I0 |
| 56.110 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s93/F |
| 56.522 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s65/I0 |
| 57.101 | 0.579 | tINS | RR | 2 | uart_byte_tx/n55_s65/F |
| 57.514 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s53/I1 |
| 58.081 | 0.567 | tINS | RR | 5 | uart_byte_tx/n55_s53/F |
| 58.494 | 0.413 | tNET | RR | 1 | uart_byte_tx/n55_s49/I1 |
| 59.061 | 0.567 | tINS | RR | 15 | uart_byte_tx/n55_s49/F |
| 59.474 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s83/I0 |
| 60.052 | 0.579 | tINS | RR | 1 | uart_byte_tx/n56_s83/F |
| 60.465 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s52/I1 |
| 61.032 | 0.567 | tINS | RR | 5 | uart_byte_tx/n56_s52/F |
| 61.445 | 0.413 | tNET | RR | 1 | uart_byte_tx/n56_s32/I0 |
| 62.024 | 0.579 | tINS | RR | 6 | uart_byte_tx/n56_s32/F |
| 62.436 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s175/I0 |
| 63.015 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s175/F |
| 63.427 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s152/I1 |
| 63.995 | 0.567 | tINS | RR | 1 | uart_byte_tx/n57_s152/F |
| 64.407 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s113/I0 |
| 64.986 | 0.579 | tINS | RR | 5 | uart_byte_tx/n57_s113/F |
| 65.399 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s80/I0 |
| 65.977 | 0.579 | tINS | RR | 2 | uart_byte_tx/n57_s80/F |
| 66.390 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s60/I0 |
| 66.969 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s60/F |
| 67.381 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s53/I0 |
| 67.960 | 0.579 | tINS | RR | 4 | uart_byte_tx/n57_s53/F |
| 68.372 | 0.413 | tNET | RR | 1 | uart_byte_tx/n57_s51/I1 |
| 68.940 | 0.567 | tINS | RR | 33 | uart_byte_tx/n57_s51/F |
| 69.352 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s110/I0 |
| 69.931 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s110/F |
| 70.344 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s78/I0 |
| 70.922 | 0.579 | tINS | RR | 3 | uart_byte_tx/n58_s78/F |
| 71.335 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s59/I0 |
| 71.914 | 0.579 | tINS | RR | 1 | uart_byte_tx/n58_s59/F |
| 72.326 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s52/I0 |
| 72.905 | 0.579 | tINS | RR | 7 | uart_byte_tx/n58_s52/F |
| 73.317 | 0.413 | tNET | RR | 1 | uart_byte_tx/n58_s50/I1 |
| 73.885 | 0.567 | tINS | RR | 23 | uart_byte_tx/n58_s50/F |
| 74.297 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 915 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_byte_tx/bps_DR_3_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_byte_tx/bps_DR_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 75 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 42.565, 57.609%; route: 30.938, 41.873%; tC2Q: 0.382, 0.518% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |