Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\FX2_CDC_7606C_fifo.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\FX2_CDC_Loopback.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\SPI_Slave.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\ad7606C_driver.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\ad7606C_soft_driver.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\adc_write_ctrl.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\cdc_cmd.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\cmd_ctrl.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_in\fifo_in.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_top\fifo_top.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fx2_send_ctrl.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\hc595_driver.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\hex8.v C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\pll_init.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV60PG484AC1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Mon Aug 18 10:51:20 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FX2_CDC_7606C_fifo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.313s, Peak memory usage = 1617.672MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.159s, Peak memory usage = 1617.672MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 1617.672MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 1617.672MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 1617.672MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 1617.672MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 1617.672MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 1617.672MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 1617.672MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 1617.672MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 1617.672MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1617.672MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.199s, Peak memory usage = 1617.672MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 1617.672MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 1617.672MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 52 |
| I/O Buf | 52 |
| IBUF | 10 |
| OBUF | 18 |
| IOBUF | 24 |
| Register | 1419 |
| DFFSE | 1 |
| DFFRE | 636 |
| DFFPE | 40 |
| DFFCE | 742 |
| LUT | 1560 |
| LUT2 | 216 |
| LUT3 | 576 |
| LUT4 | 768 |
| ALU | 201 |
| ALU | 201 |
| SSRAM | 6 |
| RAM16S4 | 6 |
| INV | 25 |
| INV | 25 |
| BSRAM | 18 |
| SDPB | 17 |
| pROM | 1 |
| CLOCK | 1 |
| PLLA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1822(1585 LUT, 201 ALU, 6 RAM16) / 59904 | 4% |
| Register | 1419 / 60780 | 3% |
| --Register as Latch | 0 / 60780 | 0% |
| --Register as FF | 1419 / 60780 | 3% |
| BSRAM | 18 / 118 | 16% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SPI_SCLK_ibuf/I | ||
| 4 | FX2_CDC_Loopback/hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_CDC_Loopback/hex8/clk_1K_s1/Q | ||
| 5 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 182.191(MHz) | 7 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 105.946(MHz) | 13 | TOP |
| 3 | SPI_SCLK | 100.000(MHz) | 289.331(MHz) | 4 | TOP |
| 4 | FX2_CDC_Loopback/hex8/clk_1K | 100.000(MHz) | 390.816(MHz) | 3 | TOP |
| 5 | Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk | 100.000(MHz) | 154.799(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.561 |
| Data Arrival Time | 9.750 |
| Data Required Time | 10.311 |
| From | fifo_top/fifo_inst/Small.rq1_wptr_0_s2 |
| To | fifo_top/fifo_inst/Almost_Empty_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rq1_wptr_0_s2/CLK |
| 0.757 | 0.382 | tC2Q | RR | 11 | fifo_top/fifo_inst/Small.rq1_wptr_0_s2/Q |
| 1.132 | 0.375 | tNET | RR | 4 | fifo_top/fifo_inst/Small.rq1_wptr_0_s14/AD[0] |
| 1.659 | 0.526 | tINS | RR | 3 | fifo_top/fifo_inst/Small.rq1_wptr_0_s14/DO[2] |
| 2.034 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_13_s0/I0 |
| 2.560 | 0.526 | tINS | RR | 3 | fifo_top/fifo_inst/Small.wcount_r_1_13_s0/F |
| 2.935 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_11_s0/I0 |
| 3.461 | 0.526 | tINS | RR | 3 | fifo_top/fifo_inst/Small.wcount_r_1_11_s0/F |
| 3.836 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_6_s0/I3 |
| 4.099 | 0.262 | tINS | RR | 6 | fifo_top/fifo_inst/Small.wcount_r_1_6_s0/F |
| 4.474 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_1_s0/I0 |
| 5.000 | 0.526 | tINS | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_1_s0/F |
| 5.375 | 0.375 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_1_s/I0 |
| 5.931 | 0.556 | tINS | RF | 1 | fifo_top/fifo_inst/rcnt_sub_1_s/COUT |
| 5.931 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/rcnt_sub_2_s/CIN |
| 5.981 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/rcnt_sub_2_s/COUT |
| 5.981 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_3_s/CIN |
| 6.031 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_3_s/COUT |
| 6.031 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_4_s/CIN |
| 6.081 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_4_s/COUT |
| 6.081 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_5_s/CIN |
| 6.131 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_5_s/COUT |
| 6.131 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_6_s/CIN |
| 6.181 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_6_s/COUT |
| 6.181 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_7_s/CIN |
| 6.231 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_7_s/COUT |
| 6.231 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_8_s/CIN |
| 6.281 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_8_s/COUT |
| 6.281 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_9_s/CIN |
| 6.331 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_9_s/COUT |
| 6.331 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_10_s/CIN |
| 6.381 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_10_s/COUT |
| 6.381 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_11_s/CIN |
| 6.431 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_11_s/COUT |
| 6.431 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_12_s/CIN |
| 6.481 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_12_s/COUT |
| 6.481 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_13_s/CIN |
| 6.531 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_13_s/COUT |
| 6.531 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_14_s/CIN |
| 6.581 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_14_s/COUT |
| 6.581 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_15_s/CIN |
| 6.825 | 0.244 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_15_s/SUM |
| 7.200 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s5/I3 |
| 7.463 | 0.262 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s5/F |
| 7.838 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s4/I3 |
| 8.100 | 0.262 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s4/F |
| 8.475 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s2/I3 |
| 8.738 | 0.262 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s2/F |
| 9.113 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s0/I3 |
| 9.375 | 0.262 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s0/F |
| 9.750 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Almost_Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Almost_Empty_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | fifo_top/fifo_inst/Almost_Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 4.867, 51.920%; route: 4.125, 44.000%; tC2Q: 0.382, 4.080% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 1.470 |
| Data Arrival Time | 3.836 |
| Data Required Time | 5.306 |
| From | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0 |
| To | FX2_CDC_Loopback/SPI_Slave/MISO_s0 |
| Launch Clk | fx2_ifclk[F] |
| Latch Clk | SPI_SCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s19/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s19/F |
| 2.034 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s17/I0 |
| 2.560 | 0.526 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s17/F |
| 2.935 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s20/I0 |
| 3.461 | 0.526 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s20/F |
| 3.836 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | SPI_SCLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | SPI_SCLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 34 | SPI_SCLK_ibuf/O |
| 5.350 | 0.350 | tNET | FF | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0/CLK |
| 5.315 | -0.035 | tUnc | FX2_CDC_Loopback/SPI_Slave/MISO_s0 | ||
| 5.306 | -0.009 | tSu | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0 |
| Clock Skew: | -0.025 |
| Setup Relationship: | 5.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 1.579, 45.612%; route: 1.500, 43.337%; tC2Q: 0.382, 11.051% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 2.246 |
| Data Arrival Time | 8.065 |
| Data Required Time | 10.311 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Empty_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.757 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.132 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.649 | 0.516 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.024 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.540 | 0.516 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 2.915 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_5_s6/I3 |
| 3.178 | 0.262 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_5_s6/F |
| 3.553 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_7_s1/I3 |
| 3.815 | 0.262 | tINS | RR | 7 | fifo_top/fifo_inst/Small.rgraynext_7_s1/F |
| 4.190 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_10_s7/I0 |
| 4.716 | 0.526 | tINS | RR | 19 | fifo_top/fifo_inst/rbin_num_next_10_s7/F |
| 5.091 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_9_s0/I1 |
| 5.608 | 0.516 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_9_s0/F |
| 5.983 | 0.375 | tNET | RR | 2 | fifo_top/fifo_inst/n316_s0/I0 |
| 6.539 | 0.556 | tINS | RF | 1 | fifo_top/fifo_inst/n316_s0/COUT |
| 6.539 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n317_s0/CIN |
| 6.589 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 6.589 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 6.639 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 6.639 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 6.689 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 6.689 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 6.739 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 6.739 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 6.789 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 7.164 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rempty_val_s1/I0 |
| 7.690 | 0.526 | tINS | RR | 1 | fifo_top/fifo_inst/rempty_val_s1/F |
| 8.065 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Empty_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | fifo_top/fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.933, 51.138%; route: 3.375, 43.888%; tC2Q: 0.382, 4.974% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 2.284 |
| Data Arrival Time | 8.000 |
| Data Required Time | 10.284 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.757 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.132 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.649 | 0.516 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.024 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.540 | 0.516 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 2.915 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_5_s6/I3 |
| 3.178 | 0.262 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_5_s6/F |
| 3.553 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_7_s1/I3 |
| 3.815 | 0.262 | tINS | RR | 7 | fifo_top/fifo_inst/Small.rgraynext_7_s1/F |
| 4.190 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_10_s7/I0 |
| 4.716 | 0.526 | tINS | RR | 19 | fifo_top/fifo_inst/rbin_num_next_10_s7/F |
| 5.091 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_9_s0/I1 |
| 5.608 | 0.516 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_9_s0/F |
| 5.983 | 0.375 | tNET | RR | 2 | fifo_top/fifo_inst/n316_s0/I0 |
| 6.539 | 0.556 | tINS | RF | 1 | fifo_top/fifo_inst/n316_s0/COUT |
| 6.539 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n317_s0/CIN |
| 6.589 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 6.589 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 6.639 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 6.639 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 6.689 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 6.689 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 6.739 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 6.739 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 6.789 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 7.164 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/n40_s1/I2 |
| 7.625 | 0.461 | tINS | RR | 16 | fifo_top/fifo_inst/n40_s1/F |
| 8.000 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s/CLKB |
| 10.284 | -0.091 | tSu | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.868, 50.722%; route: 3.375, 44.262%; tC2Q: 0.382, 5.016% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 2.284 |
| Data Arrival Time | 8.000 |
| Data Required Time | 10.284 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.757 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.132 | 0.375 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.649 | 0.516 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.024 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.540 | 0.516 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 2.915 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_5_s6/I3 |
| 3.178 | 0.262 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_5_s6/F |
| 3.553 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_7_s1/I3 |
| 3.815 | 0.262 | tINS | RR | 7 | fifo_top/fifo_inst/Small.rgraynext_7_s1/F |
| 4.190 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_10_s7/I0 |
| 4.716 | 0.526 | tINS | RR | 19 | fifo_top/fifo_inst/rbin_num_next_10_s7/F |
| 5.091 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_9_s0/I1 |
| 5.608 | 0.516 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_9_s0/F |
| 5.983 | 0.375 | tNET | RR | 2 | fifo_top/fifo_inst/n316_s0/I0 |
| 6.539 | 0.556 | tINS | RF | 1 | fifo_top/fifo_inst/n316_s0/COUT |
| 6.539 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n317_s0/CIN |
| 6.589 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 6.589 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 6.639 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 6.639 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 6.689 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 6.689 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 6.739 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 6.739 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 6.789 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 7.164 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/n40_s1/I2 |
| 7.625 | 0.461 | tINS | RR | 16 | fifo_top/fifo_inst/n40_s1/F |
| 8.000 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 743 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s/CLKB |
| 10.284 | -0.091 | tSu | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.868, 50.722%; route: 3.375, 44.262%; tC2Q: 0.382, 5.016% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |