Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_top\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\60k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Thu Aug 14 11:20:30 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.33s, Peak memory usage = 76.578MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.578MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 76.578MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.578MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.578MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 76.578MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.578MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.6s, Peak memory usage = 91.723MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 91.723MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 91.723MB
Total Time and Memory Usage CPU time = 0h 0m 0.905s, Elapsed time = 0h 0m 0.987s, Peak memory usage = 91.723MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 63
I/O Buf 63
    IBUF 21
    OBUF 42
Register 130
    DFFPE 6
    DFFCE 124
LUT 171
    LUT2 37
    LUT3 60
    LUT4 74
ALU 45
    ALU 45
SSRAM 4
    RAM16S4 4
INV 5
    INV 5
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 245(176 LUT, 45 ALU, 4 RAM16) / 59904 <1%
Register 130 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 130 / 60780 <1%
BSRAM 16 / 118 14%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 105.946(MHz) 13 TOP
2 WrClk 100.000(MHz) 170.394(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.561
Data Arrival Time 9.750
Data Required Time 10.311
From fifo_inst/Small.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 73 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 11 fifo_inst/Small.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Small.rq1_wptr_0_s14/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Small.rq1_wptr_0_s14/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_13_s0/I0
2.560 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_13_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_11_s0/I0
3.461 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_11_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_6_s0/I3
4.099 0.262 tINS RR 6 fifo_inst/Small.wcount_r_1_6_s0/F
4.474 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I0
5.000 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
5.375 0.375 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
5.931 0.556 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.931 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.981 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
5.981 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
6.031 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
6.031 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
6.081 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
6.081 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
6.131 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
6.131 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.181 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
6.181 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
6.231 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
6.231 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
6.281 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
6.281 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.331 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
6.331 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
6.381 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
6.381 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
6.431 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
6.431 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
6.481 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
6.481 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.531 0.050 tINS RR 1 fifo_inst/rcnt_sub_13_s/COUT
6.531 0.000 tNET RR 2 fifo_inst/rcnt_sub_14_s/CIN
6.581 0.050 tINS RR 1 fifo_inst/rcnt_sub_14_s/COUT
6.581 0.000 tNET RR 2 fifo_inst/rcnt_sub_15_s/CIN
6.825 0.244 tINS RR 2 fifo_inst/rcnt_sub_15_s/SUM
7.200 0.375 tNET RR 1 fifo_inst/arempty_val_s5/I3
7.463 0.262 tINS RR 1 fifo_inst/arempty_val_s5/F
7.838 0.375 tNET RR 1 fifo_inst/arempty_val_s4/I3
8.100 0.262 tINS RR 1 fifo_inst/arempty_val_s4/F
8.475 0.375 tNET RR 1 fifo_inst/arempty_val_s2/I3
8.738 0.262 tINS RR 1 fifo_inst/arempty_val_s2/F
9.113 0.375 tNET RR 1 fifo_inst/arempty_val_s0/I3
9.375 0.262 tINS RR 1 fifo_inst/arempty_val_s0/F
9.750 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 73 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.867, 51.920%; route: 4.125, 44.000%; tC2Q: 0.382, 4.080%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.111
Data Arrival Time 7.200
Data Required Time 10.311
From fifo_inst/Small.rq1_wptr_0_s2
To fifo_inst/Rnum_15_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 73 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 11 fifo_inst/Small.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Small.rq1_wptr_0_s14/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Small.rq1_wptr_0_s14/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_13_s0/I0
2.560 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_13_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_11_s0/I0
3.461 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_11_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_6_s0/I3
4.099 0.262 tINS RR 6 fifo_inst/Small.wcount_r_1_6_s0/F
4.474 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I0
5.000 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
5.375 0.375 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
5.931 0.556 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.931 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.981 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
5.981 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
6.031 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
6.031 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
6.081 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
6.081 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
6.131 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
6.131 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.181 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
6.181 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
6.231 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
6.231 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
6.281 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
6.281 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.331 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
6.331 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
6.381 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
6.381 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
6.431 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
6.431 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
6.481 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
6.481 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.531 0.050 tINS RR 1 fifo_inst/rcnt_sub_13_s/COUT
6.531 0.000 tNET RR 2 fifo_inst/rcnt_sub_14_s/CIN
6.581 0.050 tINS RR 1 fifo_inst/rcnt_sub_14_s/COUT
6.581 0.000 tNET RR 2 fifo_inst/rcnt_sub_15_s/CIN
6.825 0.244 tINS RR 2 fifo_inst/rcnt_sub_15_s/SUM
7.200 0.375 tNET RR 1 fifo_inst/Rnum_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 73 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_15_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.817, 55.934%; route: 2.625, 38.462%; tC2Q: 0.382, 5.604%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.127
Data Arrival Time 7.184
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 73 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I3
2.296 0.262 tINS RR 7 fifo_inst/rbin_num_next_5_s6/F
2.671 0.375 tNET RR 1 fifo_inst/Small.rgraynext_7_s1/I3
2.934 0.262 tINS RR 7 fifo_inst/Small.rgraynext_7_s1/F
3.309 0.375 tNET RR 1 fifo_inst/rbin_num_next_10_s7/I0
3.835 0.526 tINS RR 19 fifo_inst/rbin_num_next_10_s7/F
4.210 0.375 tNET RR 1 fifo_inst/Small.rgraynext_9_s0/I1
4.726 0.516 tINS RR 2 fifo_inst/Small.rgraynext_9_s0/F
5.101 0.375 tNET RR 2 fifo_inst/n316_s0/I0
5.658 0.556 tINS RF 1 fifo_inst/n316_s0/COUT
5.658 0.000 tNET FF 2 fifo_inst/n317_s0/CIN
5.708 0.050 tINS FR 1 fifo_inst/n317_s0/COUT
5.708 0.000 tNET RR 2 fifo_inst/n318_s0/CIN
5.758 0.050 tINS RR 1 fifo_inst/n318_s0/COUT
5.758 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
5.808 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
5.808 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
5.858 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
5.858 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
5.908 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
6.283 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
6.809 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
7.184 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 73 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.426, 50.321%; route: 3.000, 44.061%; tC2Q: 0.382, 5.618%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 3.161
Data Arrival Time 7.150
Data Required Time 10.311
From fifo_inst/Small.rq1_wptr_0_s2
To fifo_inst/Rnum_14_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 73 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 11 fifo_inst/Small.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Small.rq1_wptr_0_s14/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Small.rq1_wptr_0_s14/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_13_s0/I0
2.560 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_13_s0/F
2.935 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_11_s0/I0
3.461 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_11_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_6_s0/I3
4.099 0.262 tINS RR 6 fifo_inst/Small.wcount_r_1_6_s0/F
4.474 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I0
5.000 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
5.375 0.375 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
5.931 0.556 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.931 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.981 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
5.981 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
6.031 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
6.031 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
6.081 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
6.081 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
6.131 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
6.131 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.181 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
6.181 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
6.231 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
6.231 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
6.281 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
6.281 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.331 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
6.331 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
6.381 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
6.381 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
6.431 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
6.431 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
6.481 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
6.481 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.531 0.050 tINS RR 1 fifo_inst/rcnt_sub_13_s/COUT
6.531 0.000 tNET RR 2 fifo_inst/rcnt_sub_14_s/CIN
6.775 0.244 tINS RR 2 fifo_inst/rcnt_sub_14_s/SUM
7.150 0.375 tNET RR 1 fifo_inst/Rnum_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 73 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Rnum_14_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Rnum_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.767, 55.609%; route: 2.625, 38.745%; tC2Q: 0.382, 5.646%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.165
Data Arrival Time 7.119
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_15_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 73 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s6/I3
2.296 0.262 tINS RR 7 fifo_inst/rbin_num_next_5_s6/F
2.671 0.375 tNET RR 1 fifo_inst/Small.rgraynext_7_s1/I3
2.934 0.262 tINS RR 7 fifo_inst/Small.rgraynext_7_s1/F
3.309 0.375 tNET RR 1 fifo_inst/rbin_num_next_10_s7/I0
3.835 0.526 tINS RR 19 fifo_inst/rbin_num_next_10_s7/F
4.210 0.375 tNET RR 1 fifo_inst/Small.rgraynext_9_s0/I1
4.726 0.516 tINS RR 2 fifo_inst/Small.rgraynext_9_s0/F
5.101 0.375 tNET RR 2 fifo_inst/n316_s0/I0
5.658 0.556 tINS RF 1 fifo_inst/n316_s0/COUT
5.658 0.000 tNET FF 2 fifo_inst/n317_s0/CIN
5.708 0.050 tINS FR 1 fifo_inst/n317_s0/COUT
5.708 0.000 tNET RR 2 fifo_inst/n318_s0/CIN
5.758 0.050 tINS RR 1 fifo_inst/n318_s0/COUT
5.758 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
5.808 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
5.808 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
5.858 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
5.858 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
5.908 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
6.283 0.375 tNET RR 1 fifo_inst/n40_s1/I2
6.744 0.461 tINS RR 16 fifo_inst/n40_s1/F
7.119 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_15_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 73 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_15_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_15_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.361, 49.842%; route: 3.000, 44.486%; tC2Q: 0.382, 5.672%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%