Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\60k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_top\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\60k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Mon Aug 18 10:27:53 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.378s, Peak memory usage = 76.578MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.578MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 76.578MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 76.578MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 76.578MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.578MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 76.578MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.578MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.542s, Peak memory usage = 91.496MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 91.496MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 91.496MB
Total Time and Memory Usage CPU time = 0h 0m 0.858s, Elapsed time = 0h 0m 1s, Peak memory usage = 91.496MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 32
I/O Buf 32
    IBUF 21
    OBUF 11
Register 99
    DFFPE 6
    DFFCE 93
LUT 154
    LUT2 25
    LUT3 60
    LUT4 69
ALU 29
    ALU 29
SSRAM 4
    RAM16S4 4
INV 5
    INV 5
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 212(159 LUT, 29 ALU, 4 RAM16) / 59904 <1%
Register 99 / 60780 <1%
  --Register as Latch 0 / 60780 0%
  --Register as FF 99 / 60780 <1%
BSRAM 16 / 118 14%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 99.465(MHz) 13 TOP
2 WrClk 100.000(MHz) 188.058(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.054
Data Arrival Time 10.365
Data Required Time 10.311
From fifo_inst/Small.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Small.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 11 fifo_inst/Small.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Small.rq1_wptr_0_s14/AD[0]
1.659 0.526 tINS RR 4 fifo_inst/Small.rq1_wptr_0_s14/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_12_s1/I0
2.560 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_12_s1/F
2.935 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_12_s2/I0
3.461 0.526 tINS RR 3 fifo_inst/Small.wcount_r_1_12_s2/F
3.836 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_6_s0/I2
4.297 0.461 tINS RR 2 fifo_inst/Small.wcount_r_1_6_s0/F
4.672 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_5_s1/I0
5.199 0.526 tINS RR 5 fifo_inst/Small.wcount_r_1_5_s1/F
5.574 0.375 tNET RR 1 fifo_inst/Small.wcount_r_1_1_s0/I0
6.100 0.526 tINS RR 1 fifo_inst/Small.wcount_r_1_1_s0/F
6.475 0.375 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
7.031 0.556 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
7.031 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
7.081 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
7.081 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
7.131 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
7.131 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
7.181 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
7.181 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
7.231 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
7.231 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
7.281 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
7.281 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
7.331 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
7.331 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
7.381 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
7.381 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
7.625 0.244 tINS RR 1 fifo_inst/rcnt_sub_9_s/SUM
8.000 0.375 tNET RR 1 fifo_inst/arempty_val_s4/I1
8.516 0.516 tINS RR 1 fifo_inst/arempty_val_s4/F
8.891 0.375 tNET RR 1 fifo_inst/arempty_val_s2/I2
9.353 0.461 tINS RR 1 fifo_inst/arempty_val_s2/F
9.728 0.375 tNET RR 1 fifo_inst/arempty_val_s0/I3
9.990 0.262 tINS RR 1 fifo_inst/arempty_val_s0/F
10.365 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.482, 54.880%; route: 4.125, 41.291%; tC2Q: 0.382, 3.829%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 2.944
Data Arrival Time 7.368
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.034 0.375 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.296 0.262 tINS RR 9 fifo_inst/Small.rgraynext_4_s1/F
2.671 0.375 tNET RR 1 fifo_inst/Small.rgraynext_6_s1/I2
3.133 0.461 tINS RR 6 fifo_inst/Small.rgraynext_6_s1/F
3.508 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I2
3.969 0.461 tINS RR 2 fifo_inst/Small.rgraynext_8_s1/F
4.344 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I1
4.860 0.516 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
5.235 0.375 tNET RR 2 fifo_inst/n315_s0/I0
5.791 0.556 tINS RF 1 fifo_inst/n315_s0/COUT
5.791 0.000 tNET FF 2 fifo_inst/n316_s0/CIN
5.841 0.050 tINS FR 1 fifo_inst/n316_s0/COUT
5.841 0.000 tNET RR 2 fifo_inst/n317_s0/CIN
5.891 0.050 tINS RR 1 fifo_inst/n317_s0/COUT
5.891 0.000 tNET RR 2 fifo_inst/n318_s0/CIN
5.941 0.050 tINS RR 1 fifo_inst/n318_s0/COUT
5.941 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
5.991 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
5.991 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.041 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.041 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.091 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
6.466 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
6.993 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
7.368 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.610, 51.627%; route: 3.000, 42.903%; tC2Q: 0.382, 5.470%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 2.981
Data Arrival Time 7.303
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_15_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.034 0.375 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.296 0.262 tINS RR 9 fifo_inst/Small.rgraynext_4_s1/F
2.671 0.375 tNET RR 1 fifo_inst/Small.rgraynext_6_s1/I2
3.133 0.461 tINS RR 6 fifo_inst/Small.rgraynext_6_s1/F
3.508 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I2
3.969 0.461 tINS RR 2 fifo_inst/Small.rgraynext_8_s1/F
4.344 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I1
4.860 0.516 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
5.235 0.375 tNET RR 2 fifo_inst/n315_s0/I0
5.791 0.556 tINS RF 1 fifo_inst/n315_s0/COUT
5.791 0.000 tNET FF 2 fifo_inst/n316_s0/CIN
5.841 0.050 tINS FR 1 fifo_inst/n316_s0/COUT
5.841 0.000 tNET RR 2 fifo_inst/n317_s0/CIN
5.891 0.050 tINS RR 1 fifo_inst/n317_s0/COUT
5.891 0.000 tNET RR 2 fifo_inst/n318_s0/CIN
5.941 0.050 tINS RR 1 fifo_inst/n318_s0/COUT
5.941 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
5.991 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
5.991 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.041 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.041 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.091 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
6.466 0.375 tNET RR 1 fifo_inst/n40_s1/I2
6.928 0.461 tINS RR 16 fifo_inst/n40_s1/F
7.303 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_15_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_15_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_15_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.545, 51.173%; route: 3.000, 43.306%; tC2Q: 0.382, 5.521%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 2.981
Data Arrival Time 7.303
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_14_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.034 0.375 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.296 0.262 tINS RR 9 fifo_inst/Small.rgraynext_4_s1/F
2.671 0.375 tNET RR 1 fifo_inst/Small.rgraynext_6_s1/I2
3.133 0.461 tINS RR 6 fifo_inst/Small.rgraynext_6_s1/F
3.508 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I2
3.969 0.461 tINS RR 2 fifo_inst/Small.rgraynext_8_s1/F
4.344 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I1
4.860 0.516 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
5.235 0.375 tNET RR 2 fifo_inst/n315_s0/I0
5.791 0.556 tINS RF 1 fifo_inst/n315_s0/COUT
5.791 0.000 tNET FF 2 fifo_inst/n316_s0/CIN
5.841 0.050 tINS FR 1 fifo_inst/n316_s0/COUT
5.841 0.000 tNET RR 2 fifo_inst/n317_s0/CIN
5.891 0.050 tINS RR 1 fifo_inst/n317_s0/COUT
5.891 0.000 tNET RR 2 fifo_inst/n318_s0/CIN
5.941 0.050 tINS RR 1 fifo_inst/n318_s0/COUT
5.941 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
5.991 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
5.991 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.041 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.041 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.091 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
6.466 0.375 tNET RR 1 fifo_inst/n40_s1/I2
6.928 0.461 tINS RR 16 fifo_inst/n40_s1/F
7.303 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_14_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_14_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_14_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.545, 51.173%; route: 3.000, 43.306%; tC2Q: 0.382, 5.521%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 2.981
Data Arrival Time 7.303
Data Required Time 10.284
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_13_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 57 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.034 0.375 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.296 0.262 tINS RR 9 fifo_inst/Small.rgraynext_4_s1/F
2.671 0.375 tNET RR 1 fifo_inst/Small.rgraynext_6_s1/I2
3.133 0.461 tINS RR 6 fifo_inst/Small.rgraynext_6_s1/F
3.508 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s1/I2
3.969 0.461 tINS RR 2 fifo_inst/Small.rgraynext_8_s1/F
4.344 0.375 tNET RR 1 fifo_inst/Small.rgraynext_8_s0/I1
4.860 0.516 tINS RR 2 fifo_inst/Small.rgraynext_8_s0/F
5.235 0.375 tNET RR 2 fifo_inst/n315_s0/I0
5.791 0.556 tINS RF 1 fifo_inst/n315_s0/COUT
5.791 0.000 tNET FF 2 fifo_inst/n316_s0/CIN
5.841 0.050 tINS FR 1 fifo_inst/n316_s0/COUT
5.841 0.000 tNET RR 2 fifo_inst/n317_s0/CIN
5.891 0.050 tINS RR 1 fifo_inst/n317_s0/COUT
5.891 0.000 tNET RR 2 fifo_inst/n318_s0/CIN
5.941 0.050 tINS RR 1 fifo_inst/n318_s0/COUT
5.941 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
5.991 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
5.991 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.041 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.041 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.091 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
6.466 0.375 tNET RR 1 fifo_inst/n40_s1/I2
6.928 0.461 tINS RR 16 fifo_inst/n40_s1/F
7.303 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_13_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 57 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_13_s/CLKB
10.284 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_13_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.545, 51.173%; route: 3.000, 43.306%; tC2Q: 0.382, 5.521%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%