Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\FX2_CDC_7606C_fifo.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\FX2_CDC_Loopback.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\SPI_Slave.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\ad7606C_soft_driver.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\adc_write_ctrl.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\cdc_cmd.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\cmd_ctrl.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_in\fifo_in.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_top\fifo_top.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\hc595_driver.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\hex8.v C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\pll_init.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Fri Aug 29 14:47:58 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FX2_CDC_7606C_fifo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.267s, Peak memory usage = 277.539MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 277.539MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 277.539MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 277.539MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 277.539MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 277.539MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 277.539MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 277.539MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 277.539MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 277.539MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 277.539MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 277.539MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.264s, Peak memory usage = 277.539MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 277.539MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 277.539MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 52 |
| I/O Buf | 52 |
| IBUF | 10 |
| OBUF | 18 |
| IOBUF | 24 |
| Register | 1397 |
| DFFRE | 561 |
| DFFPE | 40 |
| DFFCE | 796 |
| LUT | 1439 |
| LUT2 | 146 |
| LUT3 | 606 |
| LUT4 | 687 |
| ALU | 198 |
| ALU | 198 |
| INV | 20 |
| INV | 20 |
| BSRAM | 17 |
| SDPB | 17 |
| CLOCK | 1 |
| PLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1657(1459 LUT, 198 ALU) / 138240 | 2% |
| Register | 1397 / 139095 | 2% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 1397 / 139095 | 2% |
| BSRAM | 17 / 340 | 5% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SPI_SCLK_ibuf/I | ||
| 4 | FX2_CDC_Loopback/hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_CDC_Loopback/hex8/clk_1K_s1/Q | ||
| 5 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | clk | Gowin_PLL/u_pll/PLL_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 207.792(MHz) | 5 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 115.191(MHz) | 10 | TOP |
| 3 | SPI_SCLK | 100.000(MHz) | 266.934(MHz) | 4 | TOP |
| 4 | FX2_CDC_Loopback/hex8/clk_1K | 100.000(MHz) | 361.011(MHz) | 3 | TOP |
| 5 | Gowin_PLL/u_pll/PLL_inst/CLKOUT0.default_gen_clk | 100.000(MHz) | 122.193(MHz) | 11 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.171 |
| Data Arrival Time | 4.170 |
| Data Required Time | 5.341 |
| From | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0 |
| To | FX2_CDC_Loopback/SPI_Slave/MISO_s0 |
| Launch Clk | fx2_ifclk[F] |
| Latch Clk | SPI_SCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s19/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s19/F |
| 2.199 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s17/I1 |
| 2.766 | 0.567 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s17/F |
| 3.179 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | SPI_SCLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | SPI_SCLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 34 | SPI_SCLK_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0/CLK |
| 5.350 | -0.035 | tUnc | FX2_CDC_Loopback/SPI_Slave/MISO_s0 | ||
| 5.341 | -0.009 | tSu | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0 |
| Clock Skew: | -0.028 |
| Setup Relationship: | 5.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 1.725, 45.908%; route: 1.650, 43.912%; tC2Q: 0.382, 10.180% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 1.319 |
| Data Arrival Time | 9.030 |
| Data Required Time | 10.349 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Empty_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.775 | 0.567 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.188 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.755 | 0.567 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 3.168 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_4_s1/I3 |
| 3.456 | 0.289 | tINS | RR | 12 | fifo_top/fifo_inst/Small.rgraynext_4_s1/F |
| 3.869 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_11_s1/I0 |
| 4.448 | 0.579 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_11_s1/F |
| 4.860 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_12_s6/I0 |
| 5.439 | 0.579 | tINS | RR | 18 | fifo_top/fifo_inst/rbin_num_next_12_s6/F |
| 5.851 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_10_s0/I1 |
| 6.419 | 0.567 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_10_s0/F |
| 6.831 | 0.413 | tNET | RR | 2 | fifo_top/fifo_inst/n317_s0/I0 |
| 7.426 | 0.595 | tINS | RF | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 7.426 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 7.476 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 7.476 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 7.526 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 7.526 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 7.576 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 7.576 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 7.626 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 8.039 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rempty_val_s1/I0 |
| 8.618 | 0.579 | tINS | RR | 1 | fifo_top/fifo_inst/rempty_val_s1/F |
| 9.030 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_top/fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.523, 52.480%; route: 3.712, 43.081%; tC2Q: 0.382, 4.439% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 1.362 |
| Data Arrival Time | 8.959 |
| Data Required Time | 10.321 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.775 | 0.567 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.188 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.755 | 0.567 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 3.168 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_4_s1/I3 |
| 3.456 | 0.289 | tINS | RR | 12 | fifo_top/fifo_inst/Small.rgraynext_4_s1/F |
| 3.869 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_11_s1/I0 |
| 4.448 | 0.579 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_11_s1/F |
| 4.860 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_12_s6/I0 |
| 5.439 | 0.579 | tINS | RR | 18 | fifo_top/fifo_inst/rbin_num_next_12_s6/F |
| 5.851 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_10_s0/I1 |
| 6.419 | 0.567 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_10_s0/F |
| 6.831 | 0.413 | tNET | RR | 2 | fifo_top/fifo_inst/n317_s0/I0 |
| 7.426 | 0.595 | tINS | RF | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 7.426 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 7.476 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 7.476 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 7.526 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 7.526 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 7.576 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 7.576 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 7.626 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 8.039 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/n40_s1/I2 |
| 8.546 | 0.507 | tINS | RR | 16 | fifo_top/fifo_inst/n40_s1/F |
| 8.959 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_15_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.451, 52.084%; route: 3.712, 43.440%; tC2Q: 0.382, 4.476% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 1.362 |
| Data Arrival Time | 8.959 |
| Data Required Time | 10.321 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.775 | 0.567 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.188 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.755 | 0.567 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 3.168 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_4_s1/I3 |
| 3.456 | 0.289 | tINS | RR | 12 | fifo_top/fifo_inst/Small.rgraynext_4_s1/F |
| 3.869 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_11_s1/I0 |
| 4.448 | 0.579 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_11_s1/F |
| 4.860 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_12_s6/I0 |
| 5.439 | 0.579 | tINS | RR | 18 | fifo_top/fifo_inst/rbin_num_next_12_s6/F |
| 5.851 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_10_s0/I1 |
| 6.419 | 0.567 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_10_s0/F |
| 6.831 | 0.413 | tNET | RR | 2 | fifo_top/fifo_inst/n317_s0/I0 |
| 7.426 | 0.595 | tINS | RF | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 7.426 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 7.476 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 7.476 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 7.526 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 7.526 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 7.576 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 7.576 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 7.626 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 8.039 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/n40_s1/I2 |
| 8.546 | 0.507 | tINS | RR | 16 | fifo_top/fifo_inst/n40_s1/F |
| 8.959 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_14_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.451, 52.084%; route: 3.712, 43.440%; tC2Q: 0.382, 4.476% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 1.362 |
| Data Arrival Time | 8.959 |
| Data Required Time | 10.321 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Small.mem_Small.mem_0_13_s |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.775 | 0.567 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.188 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s6/I1 |
| 2.755 | 0.567 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_2_s6/F |
| 3.168 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_4_s1/I3 |
| 3.456 | 0.289 | tINS | RR | 12 | fifo_top/fifo_inst/Small.rgraynext_4_s1/F |
| 3.869 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_11_s1/I0 |
| 4.448 | 0.579 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_11_s1/F |
| 4.860 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_12_s6/I0 |
| 5.439 | 0.579 | tINS | RR | 18 | fifo_top/fifo_inst/rbin_num_next_12_s6/F |
| 5.851 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_10_s0/I1 |
| 6.419 | 0.567 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_10_s0/F |
| 6.831 | 0.413 | tNET | RR | 2 | fifo_top/fifo_inst/n317_s0/I0 |
| 7.426 | 0.595 | tINS | RF | 1 | fifo_top/fifo_inst/n317_s0/COUT |
| 7.426 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n318_s0/CIN |
| 7.476 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n318_s0/COUT |
| 7.476 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n319_s0/CIN |
| 7.526 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n319_s0/COUT |
| 7.526 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n320_s0/CIN |
| 7.576 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n320_s0/COUT |
| 7.576 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n321_s0/CIN |
| 7.626 | 0.050 | tINS | RR | 2 | fifo_top/fifo_inst/n321_s0/COUT |
| 8.039 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/n40_s1/I2 |
| 8.546 | 0.507 | tINS | RR | 16 | fifo_top/fifo_inst/n40_s1/F |
| 8.959 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_13_s/CEB |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_13_s/CLKB |
| 10.321 | -0.091 | tSu | 1 | fifo_top/fifo_inst/Small.mem_Small.mem_0_13_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.451, 52.084%; route: 3.712, 43.440%; tC2Q: 0.382, 4.476% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |