Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_top\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\138k_FX2_CDC_7606C_fifo\FX2_CDC_7606C_fifo\src\fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Fri Aug 29 11:23:56 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.329s, Peak memory usage = 76.426MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.426MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.426MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.426MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 76.426MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.426MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.426MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.426MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.426MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 76.426MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.426MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.426MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.468s, Peak memory usage = 91.742MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 91.742MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 91.742MB
Total Time and Memory Usage CPU time = 0h 0m 0.81s, Elapsed time = 0h 0m 0.85s, Peak memory usage = 91.742MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 63
I/O Buf 63
    IBUF 21
    OBUF 42
Register 157
    DFFPE 6
    DFFCE 151
LUT 151
    LUT2 34
    LUT3 50
    LUT4 67
ALU 45
    ALU 45
INV 4
    INV 4
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 200(155 LUT, 45 ALU) / 138240 <1%
Register 157 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 157 / 139095 <1%
BSRAM 16 / 340 5%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 122.343(MHz) 10 TOP
2 WrClk 100.000(MHz) 158.541(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.826
Data Arrival Time 8.523
Data Required Time 10.349
From fifo_inst/Small.rq2_wptr_14_s0
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 96 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Small.rq2_wptr_14_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Small.rq2_wptr_14_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_12_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Small.wcount_r_1_12_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s0/I3
2.487 0.289 tINS RR 6 fifo_inst/Small.wcount_r_1_9_s0/F
2.900 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_3_s0/I2
3.408 0.507 tINS RR 3 fifo_inst/Small.wcount_r_1_3_s0/F
3.820 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s0/I1
4.388 0.567 tINS RR 1 fifo_inst/Small.wcount_r_1_2_s0/F
4.800 0.413 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.395 0.595 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.395 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.445 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.445 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.495 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.495 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.545 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.545 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.595 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.595 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.645 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.645 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.695 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.695 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
5.745 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
5.745 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
5.795 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
5.795 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
5.845 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
5.845 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
5.895 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
5.895 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.139 0.244 tINS RR 2 fifo_inst/rcnt_sub_13_s/SUM
6.551 0.413 tNET RR 1 fifo_inst/arempty_val_s1/I1
7.119 0.567 tINS RR 1 fifo_inst/arempty_val_s1/F
7.531 0.413 tNET RR 1 fifo_inst/arempty_val_s0/I0
8.110 0.579 tINS RR 1 fifo_inst/arempty_val_s0/F
8.523 0.413 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 96 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.427, 54.593%; route: 3.300, 40.691%; tC2Q: 0.382, 4.716%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 2.287
Data Arrival Time 8.061
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 96 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.487 0.289 tINS RR 12 fifo_inst/Small.rgraynext_4_s1/F
2.900 0.413 tNET RR 1 fifo_inst/Small.rgraynext_11_s1/I0
3.479 0.579 tINS RR 2 fifo_inst/Small.rgraynext_11_s1/F
3.891 0.413 tNET RR 1 fifo_inst/rbin_num_next_12_s6/I0
4.470 0.579 tINS RR 18 fifo_inst/rbin_num_next_12_s6/F
4.883 0.413 tNET RR 1 fifo_inst/Small.rgraynext_10_s0/I1
5.450 0.567 tINS RR 2 fifo_inst/Small.rgraynext_10_s0/F
5.863 0.413 tNET RR 2 fifo_inst/n317_s0/I0
6.458 0.595 tINS RF 1 fifo_inst/n317_s0/COUT
6.458 0.000 tNET FF 2 fifo_inst/n318_s0/CIN
6.508 0.050 tINS FR 1 fifo_inst/n318_s0/COUT
6.508 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
6.558 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
6.558 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.608 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.608 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.658 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
7.070 0.413 tNET RR 1 fifo_inst/rempty_val_s1/I0
7.649 0.579 tINS RR 1 fifo_inst/rempty_val_s1/F
8.061 0.413 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 96 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.966, 51.855%; route: 3.300, 43.144%; tC2Q: 0.382, 5.001%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 2.331
Data Arrival Time 7.990
Data Required Time 10.321
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_15_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 96 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.487 0.289 tINS RR 12 fifo_inst/Small.rgraynext_4_s1/F
2.900 0.413 tNET RR 1 fifo_inst/Small.rgraynext_11_s1/I0
3.479 0.579 tINS RR 2 fifo_inst/Small.rgraynext_11_s1/F
3.891 0.413 tNET RR 1 fifo_inst/rbin_num_next_12_s6/I0
4.470 0.579 tINS RR 18 fifo_inst/rbin_num_next_12_s6/F
4.883 0.413 tNET RR 1 fifo_inst/Small.rgraynext_10_s0/I1
5.450 0.567 tINS RR 2 fifo_inst/Small.rgraynext_10_s0/F
5.863 0.413 tNET RR 2 fifo_inst/n317_s0/I0
6.458 0.595 tINS RF 1 fifo_inst/n317_s0/COUT
6.458 0.000 tNET FF 2 fifo_inst/n318_s0/CIN
6.508 0.050 tINS FR 1 fifo_inst/n318_s0/COUT
6.508 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
6.558 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
6.558 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.608 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.608 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.658 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
7.070 0.413 tNET RR 1 fifo_inst/n40_s1/I2
7.578 0.507 tINS RR 16 fifo_inst/n40_s1/F
7.990 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_15_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 96 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_15_s/CLKB
10.321 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_15_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.895, 51.402%; route: 3.300, 43.550%; tC2Q: 0.382, 5.048%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 2.331
Data Arrival Time 7.990
Data Required Time 10.321
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_14_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 96 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.487 0.289 tINS RR 12 fifo_inst/Small.rgraynext_4_s1/F
2.900 0.413 tNET RR 1 fifo_inst/Small.rgraynext_11_s1/I0
3.479 0.579 tINS RR 2 fifo_inst/Small.rgraynext_11_s1/F
3.891 0.413 tNET RR 1 fifo_inst/rbin_num_next_12_s6/I0
4.470 0.579 tINS RR 18 fifo_inst/rbin_num_next_12_s6/F
4.883 0.413 tNET RR 1 fifo_inst/Small.rgraynext_10_s0/I1
5.450 0.567 tINS RR 2 fifo_inst/Small.rgraynext_10_s0/F
5.863 0.413 tNET RR 2 fifo_inst/n317_s0/I0
6.458 0.595 tINS RF 1 fifo_inst/n317_s0/COUT
6.458 0.000 tNET FF 2 fifo_inst/n318_s0/CIN
6.508 0.050 tINS FR 1 fifo_inst/n318_s0/COUT
6.508 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
6.558 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
6.558 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.608 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.608 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.658 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
7.070 0.413 tNET RR 1 fifo_inst/n40_s1/I2
7.578 0.507 tINS RR 16 fifo_inst/n40_s1/F
7.990 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_14_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 96 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_14_s/CLKB
10.321 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_14_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.895, 51.402%; route: 3.300, 43.550%; tC2Q: 0.382, 5.048%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 2.331
Data Arrival Time 7.990
Data Required Time 10.321
From fifo_inst/Empty_s0
To fifo_inst/Small.mem_Small.mem_0_13_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 96 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s6/I0
1.786 0.579 tINS RR 7 fifo_inst/rbin_num_next_2_s6/F
2.199 0.413 tNET RR 1 fifo_inst/Small.rgraynext_4_s1/I3
2.487 0.289 tINS RR 12 fifo_inst/Small.rgraynext_4_s1/F
2.900 0.413 tNET RR 1 fifo_inst/Small.rgraynext_11_s1/I0
3.479 0.579 tINS RR 2 fifo_inst/Small.rgraynext_11_s1/F
3.891 0.413 tNET RR 1 fifo_inst/rbin_num_next_12_s6/I0
4.470 0.579 tINS RR 18 fifo_inst/rbin_num_next_12_s6/F
4.883 0.413 tNET RR 1 fifo_inst/Small.rgraynext_10_s0/I1
5.450 0.567 tINS RR 2 fifo_inst/Small.rgraynext_10_s0/F
5.863 0.413 tNET RR 2 fifo_inst/n317_s0/I0
6.458 0.595 tINS RF 1 fifo_inst/n317_s0/COUT
6.458 0.000 tNET FF 2 fifo_inst/n318_s0/CIN
6.508 0.050 tINS FR 1 fifo_inst/n318_s0/COUT
6.508 0.000 tNET RR 2 fifo_inst/n319_s0/CIN
6.558 0.050 tINS RR 1 fifo_inst/n319_s0/COUT
6.558 0.000 tNET RR 2 fifo_inst/n320_s0/CIN
6.608 0.050 tINS RR 1 fifo_inst/n320_s0/COUT
6.608 0.000 tNET RR 2 fifo_inst/n321_s0/CIN
6.658 0.050 tINS RR 2 fifo_inst/n321_s0/COUT
7.070 0.413 tNET RR 1 fifo_inst/n40_s1/I2
7.578 0.507 tINS RR 16 fifo_inst/n40_s1/F
7.990 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_13_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 96 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.mem_Small.mem_0_13_s/CLKB
10.321 -0.091 tSu 1 fifo_inst/Small.mem_Small.mem_0_13_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.895, 51.402%; route: 3.300, 43.550%; tC2Q: 0.382, 5.048%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%