Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\FX2_CDC_7606_fifo.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\FX2_CDC_Loopback.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\SPI_Slave.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\ad7606_driver.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\adc_write_ctrl.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\cdc_cmd.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\cmd_ctrl.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_in\fifo_in.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_top\fifo_top.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fx2_send_ctrl.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\hc595_driver.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\hex8.v C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\pll_init.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV138PG484AC1/I0 |
| Device | GW5AT-138 |
| Device Version | B |
| Created Time | Fri Aug 29 15:25:27 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FX2_CDC_7606_fifo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.237s, Peak memory usage = 216.496MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 216.496MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 216.496MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 216.496MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 216.496MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 216.496MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 216.496MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 216.496MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 216.496MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 216.496MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 216.496MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 241.285MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.198s, Peak memory usage = 241.688MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 241.688MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 241.688MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 52 |
| I/O Buf | 52 |
| IBUF | 26 |
| OBUF | 18 |
| IOBUF | 8 |
| Register | 1197 |
| DFFRE | 537 |
| DFFPE | 38 |
| DFFCE | 622 |
| LUT | 1086 |
| LUT2 | 129 |
| LUT3 | 499 |
| LUT4 | 458 |
| ALU | 102 |
| ALU | 102 |
| INV | 15 |
| INV | 15 |
| BSRAM | 17 |
| SDPB | 17 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1203(1101 LUT, 102 ALU) / 138240 | <1% |
| Register | 1197 / 139095 | <1% |
| --Register as Latch | 0 / 139095 | 0% |
| --Register as FF | 1197 / 139095 | <1% |
| BSRAM | 17 / 340 | 5% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
| 2 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 3 | SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SPI_SCLK_ibuf/I | ||
| 4 | FX2_CDC_Loopback/hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | FX2_CDC_Loopback/hex8/clk_1K_s1/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.000(MHz) | 143.652(MHz) | 8 | TOP |
| 2 | fx2_ifclk | 100.000(MHz) | 112.819(MHz) | 11 | TOP |
| 3 | SPI_SCLK | 100.000(MHz) | 266.934(MHz) | 4 | TOP |
| 4 | FX2_CDC_Loopback/hex8/clk_1K | 100.000(MHz) | 361.011(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.136 |
| Data Arrival Time | 9.213 |
| Data Required Time | 10.349 |
| From | fifo_top/fifo_inst/Small.rq2_wptr_14_s0 |
| To | fifo_top/fifo_inst/Almost_Empty_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rq2_wptr_14_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 5 | fifo_top/fifo_inst/Small.rq2_wptr_14_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_12_s0/I0 |
| 1.786 | 0.579 | tINS | RR | 4 | fifo_top/fifo_inst/Small.wcount_r_1_12_s0/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_9_s0/I3 |
| 2.487 | 0.289 | tINS | RR | 6 | fifo_top/fifo_inst/Small.wcount_r_1_9_s0/F |
| 2.900 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_3_s1/I2 |
| 3.408 | 0.507 | tINS | RR | 3 | fifo_top/fifo_inst/Small.wcount_r_1_3_s1/F |
| 3.820 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_2_s0/I1 |
| 4.388 | 0.567 | tINS | RR | 1 | fifo_top/fifo_inst/Small.wcount_r_1_2_s0/F |
| 4.800 | 0.413 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_2_s/I0 |
| 5.395 | 0.595 | tINS | RF | 1 | fifo_top/fifo_inst/rcnt_sub_2_s/COUT |
| 5.395 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/rcnt_sub_3_s/CIN |
| 5.445 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/rcnt_sub_3_s/COUT |
| 5.445 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_4_s/CIN |
| 5.495 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_4_s/COUT |
| 5.495 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_5_s/CIN |
| 5.545 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_5_s/COUT |
| 5.545 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_6_s/CIN |
| 5.595 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_6_s/COUT |
| 5.595 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_7_s/CIN |
| 5.645 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_7_s/COUT |
| 5.645 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_8_s/CIN |
| 5.695 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_8_s/COUT |
| 5.695 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_9_s/CIN |
| 5.745 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_9_s/COUT |
| 5.745 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_10_s/CIN |
| 5.795 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_10_s/COUT |
| 5.795 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_11_s/CIN |
| 5.845 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_11_s/COUT |
| 5.845 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_12_s/CIN |
| 5.895 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_12_s/COUT |
| 5.895 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/rcnt_sub_13_s/CIN |
| 6.139 | 0.244 | tINS | RR | 1 | fifo_top/fifo_inst/rcnt_sub_13_s/SUM |
| 6.551 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s4/I1 |
| 7.119 | 0.567 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s4/F |
| 7.531 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s2/I3 |
| 7.820 | 0.289 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s2/F |
| 8.233 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/arempty_val_s0/I1 |
| 8.800 | 0.567 | tINS | RR | 1 | fifo_top/fifo_inst/arempty_val_s0/F |
| 9.213 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Almost_Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Almost_Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_top/fifo_inst/Almost_Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.705, 53.466%; route: 3.712, 42.187%; tC2Q: 0.382, 4.347% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 1.171 |
| Data Arrival Time | 4.170 |
| Data Required Time | 5.341 |
| From | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0 |
| To | FX2_CDC_Loopback/SPI_Slave/MISO_s0 |
| Launch Clk | fx2_ifclk[F] |
| Latch Clk | SPI_SCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/SPI_Slave/Send_Data_R_2_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s19/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s19/F |
| 2.199 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s17/I1 |
| 2.766 | 0.567 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s17/F |
| 3.179 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 1 | FX2_CDC_Loopback/SPI_Slave/n171_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | SPI_SCLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | SPI_SCLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 34 | SPI_SCLK_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0/CLK |
| 5.350 | -0.035 | tUnc | FX2_CDC_Loopback/SPI_Slave/MISO_s0 | ||
| 5.341 | -0.009 | tSu | 1 | FX2_CDC_Loopback/SPI_Slave/MISO_s0 |
| Clock Skew: | -0.028 |
| Setup Relationship: | 5.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 1.725, 45.908%; route: 1.650, 43.912%; tC2Q: 0.382, 10.180% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 1.451 |
| Data Arrival Time | 8.898 |
| Data Required Time | 10.349 |
| From | FX2_CDC_Loopback/fifordreq_r_s1 |
| To | fifo_top/fifo_inst/Empty_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | FX2_CDC_Loopback/fifordreq_r_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/fifordreq_Z_s/I1 |
| 1.775 | 0.567 | tINS | RR | 5 | FX2_CDC_Loopback/fifordreq_Z_s/F |
| 2.188 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_2_s4/I1 |
| 2.755 | 0.567 | tINS | RR | 8 | fifo_top/fifo_inst/rbin_num_next_2_s4/F |
| 3.168 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_8_s4/I1 |
| 3.735 | 0.567 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_8_s4/F |
| 4.148 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_11_s4/I3 |
| 4.436 | 0.289 | tINS | RR | 7 | fifo_top/fifo_inst/rbin_num_next_11_s4/F |
| 4.849 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rbin_num_next_12_s3/I1 |
| 5.416 | 0.567 | tINS | RR | 2 | fifo_top/fifo_inst/rbin_num_next_12_s3/F |
| 5.829 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Small.rgraynext_10_s1/I2 |
| 6.336 | 0.507 | tINS | RR | 2 | fifo_top/fifo_inst/Small.rgraynext_10_s1/F |
| 6.749 | 0.413 | tNET | RR | 2 | fifo_top/fifo_inst/n262_s0/I0 |
| 7.344 | 0.595 | tINS | RF | 1 | fifo_top/fifo_inst/n262_s0/COUT |
| 7.344 | 0.000 | tNET | FF | 2 | fifo_top/fifo_inst/n263_s0/CIN |
| 7.394 | 0.050 | tINS | FR | 1 | fifo_top/fifo_inst/n263_s0/COUT |
| 7.394 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n264_s0/CIN |
| 7.444 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n264_s0/COUT |
| 7.444 | 0.000 | tNET | RR | 2 | fifo_top/fifo_inst/n265_s0/CIN |
| 7.494 | 0.050 | tINS | RR | 1 | fifo_top/fifo_inst/n265_s0/COUT |
| 7.906 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/rempty_val_s1/I0 |
| 8.485 | 0.579 | tINS | RR | 1 | fifo_top/fifo_inst/rempty_val_s1/F |
| 8.898 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_top/fifo_inst/Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_top/fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 4.390, 51.738%; route: 3.712, 43.754%; tC2Q: 0.382, 4.508% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 2.316 |
| Data Arrival Time | 7.998 |
| Data Required Time | 10.314 |
| From | FX2_CDC_Loopback/SM_State_4_s4 |
| To | FX2_CDC_Loopback/SM_State_3_s0 |
| Launch Clk | SPI_SCLK[R] |
| Latch Clk | fx2_ifclk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | SPI_SCLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | SPI_SCLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 34 | SPI_SCLK_ibuf/O |
| 5.385 | 0.385 | tNET | FF | 1 | FX2_CDC_Loopback/SM_State_4_s4/I0 |
| 5.964 | 0.579 | tINS | FR | 3 | FX2_CDC_Loopback/SM_State_4_s4/F |
| 6.376 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/n1657_s9/I3 |
| 6.665 | 0.289 | tINS | RR | 1 | FX2_CDC_Loopback/n1657_s9/F |
| 7.078 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/n1657_s6/I2 |
| 7.585 | 0.507 | tINS | RR | 1 | FX2_CDC_Loopback/n1657_s6/F |
| 7.998 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SM_State_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 766 | fx2_ifclk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | FX2_CDC_Loopback/SM_State_3_s0/CLK |
| 10.378 | -0.035 | tUnc | FX2_CDC_Loopback/SM_State_3_s0 | ||
| 10.314 | -0.064 | tSu | 1 | FX2_CDC_Loopback/SM_State_3_s0 |
| Clock Skew: | 0.413 |
| Setup Relationship: | 5.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.375, 45.872%; route: 1.238, 41.284%; tC2Q: 0.385, 12.844% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 5
Path Summary:| Slack | 3.039 |
| Data Arrival Time | 7.310 |
| Data Required Time | 10.349 |
| From | fifo_in/fifo_inst/Empty_s0 |
| To | fifo_in/fifo_inst/Empty_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 425 | clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/Empty_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 70 | fifo_in/fifo_inst/Empty_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | n194_s2/I0 |
| 1.786 | 0.579 | tINS | RR | 6 | n194_s2/F |
| 2.199 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/rbin_num_next_2_s4/I1 |
| 2.766 | 0.567 | tINS | RR | 8 | fifo_in/fifo_inst/rbin_num_next_2_s4/F |
| 3.179 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/rbin_num_next_4_s4/I0 |
| 3.758 | 0.579 | tINS | RR | 2 | fifo_in/fifo_inst/rbin_num_next_4_s4/F |
| 4.170 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/Equal.rgraynext_3_s1/I0 |
| 4.749 | 0.579 | tINS | RR | 2 | fifo_in/fifo_inst/Equal.rgraynext_3_s1/F |
| 5.161 | 0.413 | tNET | RR | 2 | fifo_in/fifo_inst/n92_s0/I0 |
| 5.756 | 0.595 | tINS | RF | 1 | fifo_in/fifo_inst/n92_s0/COUT |
| 5.756 | 0.000 | tNET | FF | 2 | fifo_in/fifo_inst/n93_s0/CIN |
| 5.806 | 0.050 | tINS | FR | 1 | fifo_in/fifo_inst/n93_s0/COUT |
| 5.806 | 0.000 | tNET | RR | 2 | fifo_in/fifo_inst/n94_s0/CIN |
| 5.856 | 0.050 | tINS | RR | 1 | fifo_in/fifo_inst/n94_s0/COUT |
| 5.856 | 0.000 | tNET | RR | 2 | fifo_in/fifo_inst/n95_s0/CIN |
| 5.906 | 0.050 | tINS | RR | 1 | fifo_in/fifo_inst/n95_s0/COUT |
| 6.319 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/rempty_val_s1/I0 |
| 6.898 | 0.579 | tINS | RR | 1 | fifo_in/fifo_inst/rempty_val_s1/F |
| 7.310 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 425 | clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | fifo_in/fifo_inst/Empty_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | fifo_in/fifo_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.628, 52.592%; route: 2.887, 41.863%; tC2Q: 0.382, 5.545% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |