Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_in\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_in\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Fri Aug 8 14:11:09 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_in
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.328s, Peak memory usage = 66.020MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 66.020MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 66.020MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 66.020MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 66.020MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.020MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.216s, Peak memory usage = 80.742MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 80.742MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 80.742MB
Total Time and Memory Usage CPU time = 0h 0m 0.514s, Elapsed time = 0h 0m 0.603s, Peak memory usage = 80.742MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 23
I/O Buf 23
    IBUF 13
    OBUF 10
Register 68
    DFFPE 5
    DFFCE 63
LUT 51
    LUT2 12
    LUT3 15
    LUT4 24
ALU 7
    ALU 7
INV 2
    INV 2
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 60(53 LUT, 7 ALU) / 138240 <1%
Register 68 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 68 / 139095 <1%
BSRAM 1 / 340 <1%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 167.189(MHz) 7 TOP
2 WrClk 100.000(MHz) 207.308(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.019
Data Arrival Time 6.330
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.786 0.579 tINS RR 8 fifo_inst/rbin_num_next_2_s4/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_4_s4/I0
2.778 0.579 tINS RR 2 fifo_inst/rbin_num_next_4_s4/F
3.190 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_3_s1/I0
3.769 0.579 tINS RR 2 fifo_inst/Equal.rgraynext_3_s1/F
4.181 0.413 tNET RR 2 fifo_inst/n92_s0/I0
4.776 0.595 tINS RF 1 fifo_inst/n92_s0/COUT
4.776 0.000 tNET FF 2 fifo_inst/n93_s0/CIN
4.826 0.050 tINS FR 1 fifo_inst/n93_s0/COUT
4.826 0.000 tNET RR 2 fifo_inst/n94_s0/CIN
4.876 0.050 tINS RR 1 fifo_inst/n94_s0/COUT
4.876 0.000 tNET RR 2 fifo_inst/n95_s0/CIN
4.926 0.050 tINS RR 1 fifo_inst/n95_s0/COUT
5.339 0.413 tNET RR 1 fifo_inst/rempty_val_s1/I0
5.918 0.579 tINS RR 1 fifo_inst/rempty_val_s1/F
6.330 0.413 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.060, 51.711%; route: 2.475, 41.825%; tC2Q: 0.382, 6.464%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 5.176
Data Arrival Time 5.173
Data Required Time 10.349
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 35 WrClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Full_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.786 0.579 tINS RR 14 fifo_inst/Equal.wgraynext_2_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wbinnext_6_s4/I0
2.778 0.579 tINS RR 1 fifo_inst/Equal.wbinnext_6_s4/F
3.190 0.413 tNET RR 1 fifo_inst/wfull_val_s1/I0
3.769 0.579 tINS RR 1 fifo_inst/wfull_val_s1/F
4.181 0.413 tNET RR 1 fifo_inst/wfull_val_s0/I0
4.760 0.579 tINS RR 1 fifo_inst/wfull_val_s0/F
5.173 0.413 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 35 WrClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Full_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 6.168
Data Arrival Time 4.181
Data Required Time 10.349
From fifo_inst/Full_s0
To fifo_inst/Equal.wptr_4_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 35 WrClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Full_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.786 0.579 tINS RR 14 fifo_inst/Equal.wgraynext_2_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wbinnext_4_s5/I0
2.778 0.579 tINS RR 2 fifo_inst/Equal.wbinnext_4_s5/F
3.190 0.413 tNET RR 1 fifo_inst/Equal.wgraynext_4_s0/I0
3.769 0.579 tINS RR 1 fifo_inst/Equal.wgraynext_4_s0/F
4.181 0.413 tNET RR 1 fifo_inst/Equal.wptr_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 35 WrClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Equal.wptr_4_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Equal.wptr_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.736, 46.070%; route: 1.650, 43.781%; tC2Q: 0.382, 10.149%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 6.168
Data Arrival Time 4.181
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_3_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.786 0.579 tINS RR 8 fifo_inst/rbin_num_next_2_s4/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_4_s4/I0
2.778 0.579 tINS RR 2 fifo_inst/rbin_num_next_4_s4/F
3.190 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_3_s1/I0
3.769 0.579 tINS RR 2 fifo_inst/Equal.rgraynext_3_s1/F
4.181 0.413 tNET RR 1 fifo_inst/Equal.rptr_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Equal.rptr_3_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Equal.rptr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.736, 46.070%; route: 1.650, 43.781%; tC2Q: 0.382, 10.149%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 6.168
Data Arrival Time 4.181
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_4_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.786 0.579 tINS RR 8 fifo_inst/rbin_num_next_2_s4/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_4_s1/I0
2.778 0.579 tINS RR 1 fifo_inst/Equal.rgraynext_4_s1/F
3.190 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_4_s0/I0
3.769 0.579 tINS RR 2 fifo_inst/Equal.rgraynext_4_s0/F
4.181 0.413 tNET RR 1 fifo_inst/Equal.rptr_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Equal.rptr_4_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Equal.rptr_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.736, 46.070%; route: 1.650, 43.781%; tC2Q: 0.382, 10.149%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%