Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_top\temp\FIFO\fifo_define.v
C:\Users\24165\Desktop\138k_FX2_CDC_7606_fifo\FX2_CDC_7606_fifo\src\fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.03_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5AT-LV138PG484AC1/I0
Device GW5AT-138
Device Version B
Created Time Fri Aug 8 14:10:26 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 76.496MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.496MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.496MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.496MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 76.496MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.496MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.496MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.496MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.496MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 76.496MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.496MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.496MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.438s, Peak memory usage = 91.523MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 91.523MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 91.523MB
Total Time and Memory Usage CPU time = 0h 0m 0.763s, Elapsed time = 0h 0m 0.86s, Peak memory usage = 91.523MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 32
I/O Buf 32
    IBUF 21
    OBUF 11
Register 126
    DFFPE 6
    DFFCE 120
LUT 135
    LUT2 27
    LUT3 46
    LUT4 62
ALU 29
    ALU 29
INV 3
    INV 3
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 167(138 LUT, 29 ALU) / 138240 <1%
Register 126 / 139095 <1%
  --Register as Latch 0 / 139095 0%
  --Register as FF 126 / 139095 <1%
BSRAM 16 / 340 5%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 112.819(MHz) 11 TOP
2 WrClk 100.000(MHz) 172.302(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.136
Data Arrival Time 9.213
Data Required Time 10.349
From fifo_inst/Small.rq2_wptr_14_s0
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 80 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Small.rq2_wptr_14_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Small.rq2_wptr_14_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_12_s0/I0
1.786 0.579 tINS RR 4 fifo_inst/Small.wcount_r_1_12_s0/F
2.199 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_9_s0/I3
2.487 0.289 tINS RR 6 fifo_inst/Small.wcount_r_1_9_s0/F
2.900 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_3_s1/I2
3.408 0.507 tINS RR 3 fifo_inst/Small.wcount_r_1_3_s1/F
3.820 0.413 tNET RR 1 fifo_inst/Small.wcount_r_1_2_s0/I1
4.388 0.567 tINS RR 1 fifo_inst/Small.wcount_r_1_2_s0/F
4.800 0.413 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.395 0.595 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.395 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.445 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.445 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.495 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.495 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.545 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.545 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.595 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.595 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.645 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.645 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.695 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.695 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
5.745 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
5.745 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
5.795 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
5.795 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
5.845 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
5.845 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
5.895 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
5.895 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.139 0.244 tINS RR 1 fifo_inst/rcnt_sub_13_s/SUM
6.551 0.413 tNET RR 1 fifo_inst/arempty_val_s4/I1
7.119 0.567 tINS RR 1 fifo_inst/arempty_val_s4/F
7.531 0.413 tNET RR 1 fifo_inst/arempty_val_s2/I3
7.820 0.289 tINS RR 1 fifo_inst/arempty_val_s2/F
8.233 0.413 tNET RR 1 fifo_inst/arempty_val_s0/I1
8.800 0.567 tINS RR 1 fifo_inst/arempty_val_s0/F
9.213 0.413 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 80 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.705, 53.466%; route: 3.712, 42.187%; tC2Q: 0.382, 4.347%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 2.420
Data Arrival Time 7.929
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 80 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.786 0.579 tINS RR 8 fifo_inst/rbin_num_next_2_s4/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_8_s4/I1
2.766 0.567 tINS RR 7 fifo_inst/rbin_num_next_8_s4/F
3.179 0.413 tNET RR 1 fifo_inst/rbin_num_next_11_s4/I3
3.467 0.289 tINS RR 7 fifo_inst/rbin_num_next_11_s4/F
3.880 0.413 tNET RR 1 fifo_inst/rbin_num_next_12_s3/I1
4.448 0.567 tINS RR 2 fifo_inst/rbin_num_next_12_s3/F
4.860 0.413 tNET RR 1 fifo_inst/Small.rgraynext_10_s1/I2
5.368 0.507 tINS RR 2 fifo_inst/Small.rgraynext_10_s1/F
5.780 0.413 tNET RR 2 fifo_inst/n262_s0/I0
6.375 0.595 tINS RF 1 fifo_inst/n262_s0/COUT
6.375 0.000 tNET FF 2 fifo_inst/n263_s0/CIN
6.425 0.050 tINS FR 1 fifo_inst/n263_s0/COUT
6.425 0.000 tNET RR 2 fifo_inst/n264_s0/CIN
6.475 0.050 tINS RR 1 fifo_inst/n264_s0/COUT
6.475 0.000 tNET RR 2 fifo_inst/n265_s0/CIN
6.525 0.050 tINS RR 1 fifo_inst/n265_s0/COUT
6.938 0.413 tNET RR 1 fifo_inst/rempty_val_s1/I0
7.516 0.579 tINS RR 1 fifo_inst/rempty_val_s1/F
7.929 0.413 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 80 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.834, 51.006%; route: 3.300, 43.905%; tC2Q: 0.382, 5.089%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 4.196
Data Arrival Time 6.153
Data Required Time 10.349
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 78 WrClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Full_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/n34_s1/I0
1.786 0.579 tINS RR 17 fifo_inst/n34_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Small.wgraynext_1_s0/I1
2.766 0.567 tINS RR 3 fifo_inst/Small.wgraynext_1_s0/F
3.179 0.413 tNET RR 1 fifo_inst/wfull_val_s5/I0
3.758 0.579 tINS RR 1 fifo_inst/wfull_val_s5/F
4.170 0.413 tNET RR 1 fifo_inst/wfull_val_s1/I0
4.749 0.579 tINS RR 1 fifo_inst/wfull_val_s1/F
5.161 0.413 tNET RR 1 fifo_inst/wfull_val_s0/I0
5.740 0.579 tINS RR 1 fifo_inst/wfull_val_s0/F
6.153 0.413 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 78 WrClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Full_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.883, 50.218%; route: 2.475, 43.118%; tC2Q: 0.382, 6.664%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 4.509
Data Arrival Time 5.840
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Small.rptr_12_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 80 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.786 0.579 tINS RR 8 fifo_inst/rbin_num_next_2_s4/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_8_s4/I1
2.766 0.567 tINS RR 7 fifo_inst/rbin_num_next_8_s4/F
3.179 0.413 tNET RR 1 fifo_inst/rbin_num_next_11_s4/I3
3.467 0.289 tINS RR 7 fifo_inst/rbin_num_next_11_s4/F
3.880 0.413 tNET RR 1 fifo_inst/Small.rgraynext_12_s2/I1
4.448 0.567 tINS RR 4 fifo_inst/Small.rgraynext_12_s2/F
4.860 0.413 tNET RR 1 fifo_inst/Small.rgraynext_12_s0/I1
5.428 0.567 tINS RR 2 fifo_inst/Small.rgraynext_12_s0/F
5.840 0.413 tNET RR 1 fifo_inst/Small.rptr_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 80 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.rptr_12_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Small.rptr_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.570, 47.352%; route: 2.475, 45.601%; tC2Q: 0.382, 7.047%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 4.509
Data Arrival Time 5.840
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Small.rptr_13_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 80 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 5 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.786 0.579 tINS RR 8 fifo_inst/rbin_num_next_2_s4/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_8_s4/I1
2.766 0.567 tINS RR 7 fifo_inst/rbin_num_next_8_s4/F
3.179 0.413 tNET RR 1 fifo_inst/rbin_num_next_11_s4/I3
3.467 0.289 tINS RR 7 fifo_inst/rbin_num_next_11_s4/F
3.880 0.413 tNET RR 1 fifo_inst/Small.rgraynext_12_s2/I1
4.448 0.567 tINS RR 4 fifo_inst/Small.rgraynext_12_s2/F
4.860 0.413 tNET RR 1 fifo_inst/Small.rgraynext_13_s0/I1
5.428 0.567 tINS RR 2 fifo_inst/Small.rgraynext_13_s0/F
5.840 0.413 tNET RR 1 fifo_inst/Small.rptr_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 80 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Small.rptr_13_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Small.rptr_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.570, 47.352%; route: 2.475, 45.601%; tC2Q: 0.382, 7.047%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%