Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\FX2_CDC_Loopback.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\SPI_Slave.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\fifo_1024x8.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\gowin_pll\gowin_pll.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\gowin_pll\gowin_pll_mod.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\hc595_driver.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\hex8.v C:\Users\24165\Desktop\60k_FX2_CDC_Loopback\FX2_CDC_Loopback\src\pll_init.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.03 (64-bit) |
| Part Number | GW5AT-LV60PG484AC1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Fri Jul 25 11:49:38 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FX2_CDC_Loopback |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.217s, Peak memory usage = 218.281MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 218.281MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 218.281MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 218.281MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 218.281MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 218.281MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 218.281MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 218.281MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 218.281MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 218.281MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 218.281MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 242.117MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.168s, Peak memory usage = 242.117MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 242.117MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 242.117MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 29 |
| I/O Buf | 27 |
| IBUF | 8 |
| OBUF | 11 |
| IOBUF | 8 |
| Register | 722 |
| DFFRE | 457 |
| DFFPE | 8 |
| DFFCE | 257 |
| LUT | 721 |
| LUT2 | 75 |
| LUT3 | 396 |
| LUT4 | 250 |
| ALU | 52 |
| ALU | 52 |
| INV | 6 |
| INV | 6 |
| BSRAM | 1 |
| SDPB | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 779(727 LUT, 52 ALU) / 59904 | 2% |
| Register | 722 / 60780 | 2% |
| --Register as Latch | 0 / 60780 | 0% |
| --Register as FF | 722 / 60780 | 2% |
| BSRAM | 1 / 118 | <1% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | fx2_ifclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | fx2_ifclk_ibuf/I | ||
| 2 | SPI_SCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SPI_SCLK_ibuf/I | ||
| 3 | hex8/clk_1K | Base | 10.000 | 100.000 | 0.000 | 5.000 | hex8/clk_1K_s2/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | fx2_ifclk | 100.000(MHz) | 146.065(MHz) | 8 | TOP |
| 2 | SPI_SCLK | 100.000(MHz) | 289.331(MHz) | 4 | TOP |
| 3 | hex8/clk_1K | 100.000(MHz) | 381.134(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.470 |
| Data Arrival Time | 3.836 |
| Data Required Time | 5.306 |
| From | SPI_Slave/Send_Data_R_2_s0 |
| To | SPI_Slave/MISO_s0 |
| Launch Clk | fx2_ifclk[F] |
| Latch Clk | SPI_SCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | SPI_Slave/Send_Data_R_2_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 1 | SPI_Slave/Send_Data_R_2_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | SPI_Slave/n171_s20/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | SPI_Slave/n171_s20/F |
| 2.034 | 0.375 | tNET | RR | 1 | SPI_Slave/n171_s17/I0 |
| 2.560 | 0.526 | tINS | RR | 1 | SPI_Slave/n171_s17/F |
| 2.935 | 0.375 | tNET | RR | 1 | SPI_Slave/n171_s21/I0 |
| 3.461 | 0.526 | tINS | RR | 1 | SPI_Slave/n171_s21/F |
| 3.836 | 0.375 | tNET | RR | 1 | SPI_Slave/MISO_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | SPI_SCLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | SPI_SCLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 34 | SPI_SCLK_ibuf/O |
| 5.350 | 0.350 | tNET | FF | 1 | SPI_Slave/MISO_s0/CLK |
| 5.315 | -0.035 | tUnc | SPI_Slave/MISO_s0 | ||
| 5.306 | -0.009 | tSu | 1 | SPI_Slave/MISO_s0 |
| Clock Skew: | -0.025 |
| Setup Relationship: | 5.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 1.579, 45.612%; route: 1.500, 43.337%; tC2Q: 0.382, 11.051% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 2.750 |
| Data Arrival Time | 7.526 |
| Data Required Time | 10.276 |
| From | SM_State_4_s4 |
| To | SM_State_3_s0 |
| Launch Clk | SPI_SCLK[R] |
| Latch Clk | fx2_ifclk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | SPI_SCLK | |||
| 5.000 | 0.000 | tCL | FF | 1 | SPI_SCLK_ibuf/I |
| 5.000 | 0.000 | tINS | FF | 34 | SPI_SCLK_ibuf/O |
| 5.350 | 0.350 | tNET | FF | 1 | SM_State_4_s4/I0 |
| 5.876 | 0.526 | tINS | FR | 3 | SM_State_4_s4/F |
| 6.251 | 0.375 | tNET | RR | 1 | n1618_s8/I3 |
| 6.514 | 0.262 | tINS | RR | 1 | n1618_s8/F |
| 6.889 | 0.375 | tNET | RR | 1 | n1618_s6/I3 |
| 7.151 | 0.262 | tINS | RR | 1 | n1618_s6/F |
| 7.526 | 0.375 | tNET | RR | 1 | SM_State_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | SM_State_3_s0/CLK |
| 10.340 | -0.035 | tUnc | SM_State_3_s0 | ||
| 10.276 | -0.064 | tSu | 1 | SM_State_3_s0 |
| Clock Skew: | 0.375 |
| Setup Relationship: | 5.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 1.051, 41.613%; route: 1.125, 44.532%; tC2Q: 0.350, 13.855% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 3
Path Summary:| Slack | 3.154 |
| Data Arrival Time | 7.157 |
| Data Required Time | 10.311 |
| From | delay_cnt_10_s0 |
| To | delay_cnt_0_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | delay_cnt_10_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 5 | delay_cnt_10_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | n170_s5/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | n170_s5/F |
| 2.034 | 0.375 | tNET | RR | 1 | n170_s1/I0 |
| 2.560 | 0.526 | tINS | RR | 4 | n170_s1/F |
| 2.935 | 0.375 | tNET | RR | 1 | n164_s2/I0 |
| 3.461 | 0.526 | tINS | RR | 2 | n164_s2/F |
| 3.836 | 0.375 | tNET | RR | 1 | n164_s0/I0 |
| 4.362 | 0.526 | tINS | RR | 2 | n164_s0/F |
| 4.737 | 0.375 | tNET | RR | 1 | delay_en_s6/I1 |
| 5.254 | 0.516 | tINS | RR | 1 | delay_en_s6/F |
| 5.629 | 0.375 | tNET | RR | 1 | delay_en_s5/I3 |
| 5.891 | 0.262 | tINS | RR | 32 | delay_en_s5/F |
| 6.266 | 0.375 | tNET | RR | 1 | n129_s2/I1 |
| 6.782 | 0.516 | tINS | RR | 1 | n129_s2/F |
| 7.157 | 0.375 | tNET | RR | 1 | delay_cnt_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | delay_cnt_0_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | delay_cnt_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.400, 50.129%; route: 3.000, 44.231%; tC2Q: 0.382, 5.640% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 3.209 |
| Data Arrival Time | 7.102 |
| Data Required Time | 10.311 |
| From | delay_cnt_10_s0 |
| To | delay_cnt_1_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | delay_cnt_10_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 5 | delay_cnt_10_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | n170_s5/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | n170_s5/F |
| 2.034 | 0.375 | tNET | RR | 1 | n170_s1/I0 |
| 2.560 | 0.526 | tINS | RR | 4 | n170_s1/F |
| 2.935 | 0.375 | tNET | RR | 1 | n164_s2/I0 |
| 3.461 | 0.526 | tINS | RR | 2 | n164_s2/F |
| 3.836 | 0.375 | tNET | RR | 1 | n164_s0/I0 |
| 4.362 | 0.526 | tINS | RR | 2 | n164_s0/F |
| 4.737 | 0.375 | tNET | RR | 1 | delay_en_s6/I1 |
| 5.254 | 0.516 | tINS | RR | 1 | delay_en_s6/F |
| 5.629 | 0.375 | tNET | RR | 1 | delay_en_s5/I3 |
| 5.891 | 0.262 | tINS | RR | 32 | delay_en_s5/F |
| 6.266 | 0.375 | tNET | RR | 1 | n128_s1/I2 |
| 6.727 | 0.461 | tINS | RR | 1 | n128_s1/F |
| 7.102 | 0.375 | tNET | RR | 1 | delay_cnt_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | delay_cnt_1_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | delay_cnt_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.345, 49.721%; route: 3.000, 44.593%; tC2Q: 0.382, 5.686% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 3.209 |
| Data Arrival Time | 7.102 |
| Data Required Time | 10.311 |
| From | delay_cnt_10_s0 |
| To | delay_cnt_4_s0 |
| Launch Clk | fx2_ifclk[R] |
| Latch Clk | fx2_ifclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | fx2_ifclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | delay_cnt_10_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 5 | delay_cnt_10_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | n170_s5/I0 |
| 1.659 | 0.526 | tINS | RR | 1 | n170_s5/F |
| 2.034 | 0.375 | tNET | RR | 1 | n170_s1/I0 |
| 2.560 | 0.526 | tINS | RR | 4 | n170_s1/F |
| 2.935 | 0.375 | tNET | RR | 1 | n164_s2/I0 |
| 3.461 | 0.526 | tINS | RR | 2 | n164_s2/F |
| 3.836 | 0.375 | tNET | RR | 1 | n164_s0/I0 |
| 4.362 | 0.526 | tINS | RR | 2 | n164_s0/F |
| 4.737 | 0.375 | tNET | RR | 1 | delay_en_s6/I1 |
| 5.254 | 0.516 | tINS | RR | 1 | delay_en_s6/F |
| 5.629 | 0.375 | tNET | RR | 1 | delay_en_s5/I3 |
| 5.891 | 0.262 | tINS | RR | 32 | delay_en_s5/F |
| 6.266 | 0.375 | tNET | RR | 1 | n125_s1/I2 |
| 6.727 | 0.461 | tINS | RR | 1 | n125_s1/F |
| 7.102 | 0.375 | tNET | RR | 1 | delay_cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | fx2_ifclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | fx2_ifclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 684 | fx2_ifclk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | delay_cnt_4_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | delay_cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.345, 49.721%; route: 3.000, 44.593%; tC2Q: 0.382, 5.686% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |